The reduction in transistor count has long been a big challenge and an ongoing objective in the design of Ternary Full Adders (TFAs). Capacitive Threshold Logic (CTL) is a well-known logic style requiring a small number of transistors to implement a circuit. This paper presents a novel CTL TFA that utilizes only 21 transistors, three of which function as capacitors. Reducing the number of transistors can achieve a more compact adder cell with fewer internal wires. Simulations by HSPICE and 32nm CNFET technology demonstrate promising results for the new TFA compared to previous competitors. It produces the output carry at the fastest speed and also utilizes six fewer transistors and three fewer nets than its closest competitor with the fewest elements. When a comprehensive evaluation factor including delay, power, and area is considered, the proposed design exhibits a performance superiority of 45.1% and 21.4% compared to the previous top-performing CTL and non-CTL designs, respectively.

中文翻译：

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基于电容阈值逻辑和碳纳米管 FET 的 21T 三进制全加器

长期以来，晶体管数量的减少一直是三进制全加器 (TFA) 设计中的一大挑战和持续目标。电容阈值逻辑 (CTL) 是一种众所周知的逻辑风格，需要少量晶体管来实现电路。本文提出了一种新颖的 CTL TFA，仅使用 21 个晶体管，其中三个用作电容器。减少晶体管的数量可以用更少的内部电线实现更紧凑的加法器单元。 HSPICE 和 32nm CNFET 技术的模拟表明，与之前的竞争对手相比，新型 TFA 具有令人鼓舞的结果。它以最快的速度产生输出进位，并且与元件最少的最接近的竞争对手相比，它使用的晶体管数量少了 6 个，网络数量也少了 3 个。当考虑延迟、功耗和面积等综合评估因素时，与之前表现最好的 CTL 和非 CTL 设计相比，所提出的设计分别表现出 45.1% 和 21.4% 的性能优势。