This paper presents an effective -architectural design method, called ExTern, to enhance the performance of a RISC-V processor experiencing computation bottlenecks. ExTern involves integrating Canonical Signed Digit (CSD) representation, a ternary number system enabling carry/borrow-free addition/subtraction in constant time , into the RISC-V processor, particularly into the execution stage. Furthermore, it adopts an extended six-stage pipeline architecture to maximize employed encoding benefits, leading to more improvement in overall execution time and throughput. Despite the presence of optimized circuits, such as fast carry chain (CARRY4) modules for binary encoding on FPGA, the customized processor applying ExTern, RISC-VT, showcases remarkable improvement in computation performance. Experimental results demonstrate a 34.3% (12.2%) improvement in working frequency leading to a lower 31% (11.5%) execution time and a 32% (12%) increase in throughput compared to a State-of-the-Art open-source five(six)-stage RISC-V processor.

中文翻译：

---

ExTern：使用三进制编码提升 RISC-V 核心性能

本文提出了一种有效的架构设计方法，称为 ExTern，以增强遇到计算瓶颈的 RISC-V 处理器的性能。 ExTern 涉及将规范符号数字 (CSD) 表示法（一种能够在恒定时间内进行无进位/借位加法/减法的三进制数字系统）集成到 RISC-V 处理器中，特别是集成到执行阶段。此外，它采用扩展的六级管道架构，以最大限度地发挥编码优势，从而进一步提高整体执行时间和吞吐量。尽管存在优化电路，例如用于在 FPGA 上进行二进制编码的快速进位链（CARRY4）模块，但应用 ExTern、RISC-VT 的定制处理器在计算性能方面表现出了显着的改进。实验结果表明，与最先进的开源软件相比，工作频率提高了 34.3% (12.2%)，执行时间缩短了 31% (11.5%)，吞吐量提高了 32% (12%)五（六）级 RISC-V 处理器。