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Mobility-Aware Utility Maximization in Digital Twin-Enabled Serverless Edge Computing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-16 Jing Li, Song Guo, Weifa Liang, Jianping Wang, Quan Chen, Wenchao Xu, Kang Wei, Xiaohua Jia
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Raptor-T: A Fused and Memory-Efficient Sparse Transformer for Long and Variable-Length Sequences IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-16 Hulin Wang, Donglin Yang, Yaqi Xia, Zheng Zhang, Qigang Wang, Jianping Fan, Xiaobo Zhou, Dazhao Cheng
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Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-15 Matteo Perotti, Matheus Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
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Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-10 Abhijit Das, Enrico Russo, Maurizio Palesi
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Construction of Reed-Solomon Erasure Codes with Four Parities Based on Systematic Vandermonde Matrices IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-10 Leilei Yu, Yunghsiang S. Han
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COALA: A Compiler-Assisted Adaptive Library Routines Allocation Framework for Heterogeneous Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-09 Qinyun Cai, Guanghua Tan, Wangdong Yang, Xianhao He, Yuwei Yan, Keqin Li, Kenli Li
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Hybrid-Memcached: A Novel Approach for Memcached Persistence Optimization with Hybrid Memory IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-09 Zhang Jiang, Xianduo Li, Tianxiang Peng, Haoran Li, Jingxuan Hong, Jin Zhang, Xiaoli Gong
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LAC: A Workload Intensity-aware Caching Scheme for High-Performance SSDs IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-09 Hui Sun, Haoqiang Tong, Yinliang Yue, Xiao Qin
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Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
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LogSay: An Efficient Comprehension System for Log Numerical Reasoning IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Jiaxing Qi, Zhongzhi Luan, Shaohan Huang, Carol Fung, Hailong Yang
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Incendio: Priority-based Scheduling for Alleviating Cold Start in Serverless Computing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Xinquan Cai, Qianlong Sang, Chuang Hu, Yili Gong, Kun Suo, Xiaobo Zhou, Dazhao Cheng
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Analysis and Mitigation of Shared Resource Contention on Heterogeneous Multicore: An Industrial Case Study IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Michael Bechtel, Heechul Yun
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vKernel: Enhancing Container Isolation via Private Code and Data IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Hang Huang, Honglei Wang, Jia Rao, Song Wu, Hao Fan, Chen Yu, Hai Jin, Kun Suo, Lisong Pan
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Error-Detection Schemes for Analog Content-Addressable Memories IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Ron M. Roth
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Multi-grained Trace Collection, Analysis, and Management of Diverse Container Images IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-08 Zhuo Huang, Qi Zhang, Hao Fan, Weibin Xue, Song Wu, Chen Yu, Hai Jin, Jun Deng, Jing Gu, Zhimin Tang
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Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-04-02 Eric Guthmuller, César Fuguet, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, Ihsane Tahir, Yves Durand
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Decentralized Task Offloading in Edge Computing: An Offline-to-Online Reinforcement Learning Approach IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-19 Hongcai Lin, Lei Yang, Hao Guo, Jiannong Cao
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An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-18 Keisuke Sugiura, Hiroki Matsutani
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Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-18 David Mallasén, Alberto A. Del Barrio, Manuel Prieto-Matias
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Reordering and Compression for Hypergraph Processing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-18 Yu Liu, Qi Luo, Mengbai Xiao, Dongxiao Yu, Huashan Chen, Xiuzhen Cheng
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HPDK: A Hybrid PM-DRAM Key-Value Store for High I/O Throughput IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-18 Bihui Liu, Zhenyu Ye, Qiao Hu, Yupeng Hu, Yuchong Hu, Yang Xu, Keqin Li
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Prefender: A Prefetching Defender against Cache Side Channel Attacks as A Pretender IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-18 Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang
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A Dynamic Adaptive Framework for Practical Byzantine Fault Tolerance Consensus Protocol in the Internet of Things IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-18 Chunpei Li, Wangjie Qiu, Xianxian Li, Chen Liu, Zhiming Zheng
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FPGA-Accelerated Range-Limited Molecular Dynamics IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Chunshu Wu, Chen Yang, Sahan Bandara, Tong Geng, Anqi Guo, Pouya Haghi, Ang Li, Martin Herbordt
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Un-IOV: Achieving Bare-metal Level I/O Virtualization Performance for Cloud Usage with Migratability, Scalability and Transparency IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Zongpu Zhang, Chenbo Xia, Cunming Liang, Jian Li, Chen Yu, Tiwei Bie, Roberts Martin, Daly Dan, Xiao Wang, Yong Liu, Haibing Guan
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AdaptMD: Balancing Space and Performance in NUMA Architectures with Adaptive Memory Deduplication IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Lulu Yao, Yongkun Li, Patrick P. C. Lee, Xiaoyang Wang, Yinlong Xu
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ElasticDNN: On-device Neural Network Remodeling for Adapting Evolving Vision Domains at Edge IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Qinglong Zhang, Rui Han, Chi Harold Liu, Guoren Wang, Lydia Y. Chen
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Randomize the running function when it is disclosed IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-04 YongGang Li, Yu Bao, Yeh-Ching Chung
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Improved Fault Analysis on Subterranean 2.0 IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-04 Sandip Kumar Mondal, Prakash Dey, Himadry Sekhar Roy, Avishek Adhikari, Subhamoy Maitra
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A Computing-in-Memory-based One-Class Hyperdimensional Computing Model for Outlier Detection IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-01 Ruixuan Wang, Sabrina Hassan Moon, X. Sharon Hu, Xun Jiao, Dayane Reis
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Monotonicity of Multi-Term Floating-Point Adders IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Mantas Mikaitis
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On the Security of Quotient Filters: Attacks and Potential Countermeasures IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Pedro Reviriego, Miguel González, Niv Dayan, Gabriel Huecas, Shanshan Liu, Fabrizio Lombardi
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GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han
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$\mathcal{O}(n)$O(n) Key–Value Sort With Active Compute Memory IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Pouya Esmaili-Dokht, Miquel Guiot, Petar Radojković, Xavier Martorell, Eduard Ayguadé, Jesus Labarta, Jason Adlard, Paolo Amato, Marco Sforzin
We propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key–value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one addressing protocol (perspective) and reading it back with different perspective. The first perspective is conventional, based on the data address; the second perspective is the sorted
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UniSched: A Unified Scheduler for Deep Learning Training Jobs with Different User Demands IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Wei Gao, Zhisheng Ye, Peng Sun, Tianwei Zhang, Yonggang Wen
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Single-Domain Generalized Predictor for Neural Architecture Search System IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-15 Lianbo Ma, Haidong Kang, Guo Yu, Qing Li, Qiang He
Performance predictors are used to reduce architecture evaluation costs in neural architecture search, which however suffers from a large amount of budget consumption in annotating substantial architectures trained from scratch. Hence, how to leverage existing annotated architectures to train a generalized predictor to find the optimal architecture on unseen target search spaces becomes a new research
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NDRec: A Near-Data Processing System for Training Large-Scale Recommendation Models IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-15 Shiyu Li, Yitu Wang, Edward Hanson, Andrew Chang, Yang Seok Ki, Hai Li, Yiran Chen
Recent advances in deep neural networks (DNNs) have enabled highly effective recommendation models for diverse web services. In such DNN-based recommendation models, the embedding layer comprises the majority of model parameters. As these models scale rapidly, the embedding layer's memory capacity and bandwidth requirements threaten to exceed the limits of current computing architectures. We observe
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GateKeeper-GPU: Fast and Accurate Pre-Alignment Filtering in Short Read Mapping IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Zülal Bingöl, Mohammed Alser, Onur Mutlu, Ozcan Ozturk, Can Alkan
At the last step of short read mapping, the candidate locations of the reads on the reference genome are verified to compute their differences from the corresponding reference segments using sequence alignment algorithms. Calculating the similarities and differences between two sequences is still computationally expensive since approximate string matching techniques traditionally inherit dynamic programming
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Accelerating Sparse DNNs Based on Tiled GEMM IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Cong Guo, Fengchen Xue, Jingwen Leng, Yuxian Qiu, Yue Guan, Weihao Cui, Quan Chen, Minyi Guo
Network pruning can reduce the computation cost of deep neural network (DNN) models. However, sparse models often produce randomly-distributed weights to maintain accuracy, leading to irregular computations. Consequently, unstructured sparse models cannot achieve meaningful speedup on commodity hardware built for dense matrix computations. Accelerators are usually modified or designed with structured
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NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Yucong Chen, Yanshan Tian, Rui Zhou, Diego Martínez Castro, Deke Guo, Qingguo Zhou
Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate within these specialized environments. Traditional RNGs in GNU/Linux systems derive entropy from peripheral
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TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Jie-Fang Zhang, Cheng-Hsun Lu, Zhengya Zhang
The continuous growth of deep neural network model size and complexity hinders the adoption of large models in resource-constrained platforms. Tensor decomposition has been shown effective in reducing the model size by large compression ratios, but the resulting tensorized neural networks (TNNs) require complex and versatile tensor shaping for tensor contraction, causing a low processing efficiency
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A Detailed Historical and Statistical Analysis of the Influence of Hardware Artifacts on SPEC Integer Benchmark Performance IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Yueyao Wang, Samuel Furman, Nicolas Hardy, Margaret Ellis, Godmar Back, Yili Hong, Kirk Cameron
The Standard Performance Evaluation Corporation (SPEC) CPU benchmark has been widely used as a measure of computing performance for decades. The SPEC is an industry-standardized, CPU-intensive benchmark suite and the collective data provide a proxy for the history of worldwide CPU and system performance. Past efforts have not provided or enabled answers to questions such as, how has the SPEC benchmark
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Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Philippos Papaphilippou, Thiem Van Chu
Network-on-chips (NoCs) are currently a widely used approach for achieving scalability of multi-cores to many-cores, as well as for interconnecting other vital system-on-chip (SoC) components. Each entity in 2D mesh-based NoCs has a router responsible for forwarding packets between the dimensions as well as the entity itself, and it is essentially a 5-port switch. With respect to the routing algorithm
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Efficient Execution of Arbitrarily Complex Cross-Shard Contracts for Blockchain Sharding IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Jianting Zhang, Wuhui Chen, Zicong Hong, Gang Xiao, Linlin Du, Zibin Zheng
Sharding is a promising solution to enhance the scalability of blockchain. However, previous sharding systems adopt the lock-based cross-shard protocol to exclusively handle one-shot cross-shard transactions, leading to low-efficiency executions and unavailable calls when handling complex cross-shard contracts that introduce multi-shot cross-shard transactions to invoke multiple contracts managed by
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TIE: Fast Experiment-Driven ML-Based Configuration Tuning for In-Memory Data Analytics IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Chao Chen, Jinhan Xin, Zhibin Yu
Recently, experiment-driven machine-learning (ML) based configuration tuning for in-memory data analytics such as Apache Spark become popular because they can achieve high speedups. However, experiment-driven ML-based approaches naturally need a large number of iterations and each iteration generates a configuration with a probabilistic strategy and executes the program on a real cluster with the configuration
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I/O Causality Based In-Line Data Deduplication for Non-Volatile Memory Enabled Storage Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Haikun Liu, Xiaozhong Jin, Chencheng Ye, Xiaofei Liao, Hai Jin, Yu Zhang
Data deduplication technologies are widely exploited to reduce capacity demands for storage. Previous chunk-based offline deduplication technologies often cause serious performance overhead due to data chunking and indexing. Particularly, they are not efficient for non-volatile memory (NVM) based storage systems because they cannot fully exploit the byte-addressability feature of NVMs for fine-grained
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BFT-DSN: A Byzantine Fault-Tolerant Decentralized Storage Network IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Hechuan Guo, Minghui Xu, Jiahao Zhang, Chunchi Liu, Rajiv Ranjan, Dongxiao Yu, Xiuzhen Cheng
With the rapid development of blockchain and its applications, the amount of data stored on decentralized storage networks (DSNs) has grown exponentially. DSNs bring together affordable storage resources from around the world to provide robust, decentralized storage services for tens of thousands of decentralized applications (dApps). However, existing DSNs do not offer verifiability when implementing
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Breaking the DECT Standard Cipher With Lower Time Cost IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Lin Ding, Zhengting Li, Ziyu Guan, Xinhai Wang, Zheng Wu
The DECT Standard Cipher (DSC) is a proprietary stream cipher used for encryption in the Digital Enhanced Cordless Telecommunications (DECT), which is a standard for short range cordless communication and widely deployed worldwide both in residential and enterprise environments. New weaknesses of the DSC stream cipher which are not discovered in previous works are explored and analyzed in this paper
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The Design of a Lossless Deduplication Scheme to Eliminate Fine-Grained Redundancy for JPEG Image Storage Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-07 Cai Deng, Xiangyu Zou, Qi Chen, Bo Tang, Wen Xia
Image data storage has grown explosively, so image deduplication is used to save storage by eliminating redundancy between different images. However, traditional image deduplication cannot eliminate fine-grained redundancy nor guarantee lossless results. In this work, we propose imDedup, a lossless and fine-grained deduplication scheme for JPEG image storage systems. Specifically, imDedup uses a novel
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Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-05 Shihang Wang, Xingbo Wang, Zhiyuan Xu, Bingzhen Chen, Chenxi Feng, Qi Wang, Terry Tao Ye
Benefit from the custom instruction extension capabilities, RISC-V architecture can be optimized for many domain-specific applications. In this paper, we propose seven RISC-V SIMD (single instruction multiple data) custom instructions that can significantly optimize the convolution, activation and pool operations in CNN inference computation. More specifically, instruction CONV23 can greatly speed
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Achieving DRAM-Like PCM by Trading Off Capacity for Latency IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-26 Irina Alam, Puneet Gupta
Phase Change Memory (PCM) is considered one of the most promising scalable non-volatile main memory alternatives to DRAM. It provides $\sim$ 4x-5x cost per bit advantage over DRAM, thus enabling cost-effective dense main memory solution. However, PCM accesses are slower than DRAM, which leads to significantly poorer overall system performance (upto 80% higher execution time for memory intensive applications
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Towards Secure Runtime Customizable Trusted Execution Environment on FPGA-SoC IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-22 Yanling Wang, Xiaolin Chang, Haoran Zhu, Jianhua Wang, Yanwei Gong, Lin Li
Processing sensitive data and deploying well-designed Intellectual Property (IP) cores on remote Field Programmable Gate Array (FPGA) are prone to private data leakage and IP theft. One effective solution is constructing Trusted Execution Environment (TEE) and its secure boot process on FPGA-SoC (FPGA System on Chip). This paper aims to establish Secure Runtime Customizable TEE (SrcTEE) on FPGA-SoC
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Blockchain-Based Portable Authenticated Data Transmission for Mobile Edge Computing: A Universally Composable Secure Solution IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-22 Shiyu Li, Yuan Zhang, Yaqing Song, Nan Cheng, Kan Yang, Hongwei Li
In mobile edge computing (MEC) systems, data is frequently transmitted between MEC servers and users holding mobile devices for supporting related services. However, critical threats towards data confidentiality and authenticity are raised: adversaries always attempt to extract data content from the transmission and impersonate others to spread malicious data for profits. Furthermore, users have to
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Distributed Program Deployment for Resource-Aware Programmable Switches IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Fuliang Li, Songlin Chen, Xingxin Jia, Chengxi Gao, Pengfei Wang, Xingwei Wang, Jiannong Cao
Programmable switches allow data plane to program how packets are processed, which enables flexibility for network management tasks, e.g., packet scheduling and flow measurement. Existing studies focus on program deployment at a single switch, while deployment across the whole data plane is still a challenging issue, especially manifested in the difficulty in joint correct implementation of P4 programs
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Distributed Multihop Task Offloading in Massive Heterogeneous IoT Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Wenjie Huang, Zhiwei Zhao, Geyong Min, Jiajun Chen
Edge computing is an emerging technology to satisfy time-varying demands of computation-intensive applications of Internet of Things (IoT) devices. Multi-hop task offloading is one of the key techniques to provide edge services to areas with poor server coverage via multi-hop task forwarding. However, the existing multi-hop offloading approaches have primarily assumed that complete information can
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Value of Information: A Comprehensive Metric for Client Selection in Federated Edge Learning IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Yifei Zou, Shikun Shen, Mengbai Xiao, Peng Li, Dongxiao Yu, Xiuzhen Cheng
Federated edge learning (FEEL) is a novel paradigm that enables privacy-preserving and distributed machine learning on end devices. However, FEEL faces challenges from data/system heterogeneity among the participating clients and resource constraints of edge networks, which affect the efficiency and accuracy of the learning process. In this paper, we propose a comprehensive framework for client selection
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Distributed Learning for Large-Scale Models at Edge With Privacy Protection IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Yuan Yuan, Shuzhen Chen, Dongxiao Yu, Zengrui Zhao, Yifei Zou, Lizhen Cui, Xiuzhen Cheng
Big data and strong computing power have promoted artificial intelligence to the era of big models. In particular, ChatGPT's debut heralded the vigorous development of large models. It is an urgent problem to train large models with trillion-level parameters efficiently. Traditional single-machine training stores all data and model parameters in memory. However, due to the limitation of memory and
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Game-Based Adaptive FLOPs and Partition Point Decision Mechanism With Latency and Energy-Efficient Tradeoff for Edge Intelligence IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-15 Xin Niu, Yajing Huang, Zhiwei Wang, Chen Yu, Hai Jin
As the product of the combination of edge computing and artificial intelligence, edge intelligence (EI) not only solves the problem of insufficient computing capacity of the end device, but also can provide users with various types of intelligent services. However, offline and online model partitioning methods respectively have problems of poor adaptability to the real computing environment and delayed
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FedRFQ: Prototype-Based Federated Learning With Reduced Redundancy, Minimal Failure, and Enhanced Quality IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-12 Biwei Yan, Hongliang Zhang, Minghui Xu, Dongxiao Yu, Xiuzhen Cheng
Federated learning is a powerful technique that enables collaborative learning among different clients. Prototype-based federated learning is a specific approach that improves the performance of local models by integrating class prototypes. However, prototype-based federated learning faces several challenges, such as prototype redundancy and prototype failure, which can limit its accuracy. In addition
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FaaSBatch: Boosting Serverless Efficiency With In-Container Parallelism and Resource Multiplexing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-11 Zhaorui Wu, Yuhui Deng, Yi Zhou, Jie Li, Shujie Pang, Xiao Qin
With high scalability and flexibility, serverless computing is becoming the most promising computing model. Existing serverless computing platforms initiate a container for each function invocation, which leads to a huge waste of computing resources. Our examinations reveal that (i) executing invocations concurrently within a single container can provide comparable performance to that provided by multiple