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The First Direct Mesh-to-Mesh Photonic Fabric IEEE Micro (IF 3.6) Pub Date : 2024-04-19 Jason Howard, Joshua B. Fryman, Shamsul Abedin
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Beyond Wires: The Future of Interconnects IEEE Micro (IF 3.6) Pub Date : 2024-04-05 Hsien-Hsin S. Lee
This issue introduces a selection of outstanding papers originally presented at Hot Interconnects (HotI-30) in 2023 and features an article from Meta Reality Labs exploring the use of compute-in-memory for AR/VR applications.
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Special Issue on Hot Interconnects 30 IEEE Micro (IF 3.6) Pub Date : 2024-04-05 Scott Levy, Whit Schonbein
The IEEE Hot Interconnects Symposium celebrated its 30th year in 2023 with an exceptional series of presentations from industry and academia on the design, implementation, and effective use of high-performance interconnects. A core role of the Symposium is to promote the dissemination of cutting-edge research in the field. To this end, the 2023 Symposium included eight peer-reviewed presentations.
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Party Like It’s 1999? IEEE Micro (IF 3.6) Pub Date : 2024-04-05 Shane Greenstein
Generative AI has created a gold rush today, but that rush has not yet grown into either a productivity boom or a financial bubble. There are good reasons to think this rush could become either one. Some productivity gains seems likely, but the emergence of a financial bubble is more difficult to predict. Do today's conditions resemble those that created a bubble in the late 1990s? We consider a few
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Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part IX: Patent Families IEEE Micro (IF 3.6) Pub Date : 2024-04-03 Joshua J. Yi
This article is the next article in the series on the patenting behavior and characteristics of computer architecture companies. This article continues to analyze the characteristics for patent families.
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Management of TinyML Enabled Internet of Things Devices IEEE Micro (IF 3.6) Pub Date : 2024-03-29 Tomasz Szydlo, Marcin Nagy
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AI and Memory Wall IEEE Micro (IF 3.6) Pub Date : 2024-03-25 Amir Gholami, Zhewei Yao, Sehoon Kim, Coleman Hooper, Michael W. Mahoney, Kurt Keutzer
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The Breakthrough Memory Solutions for Improved Performance on LLM Inference IEEE Micro (IF 3.6) Pub Date : 2024-03-25 Byeongho Kim, Sanghoon Cha, Sangsoo Park, Jieun Lee, Sukhan Lee, Shin-haeng Kang, Jinin So, Kyungsoo Kim, Jin Jung, Jong-Geon Lee, Hyeonsu Kim, Jin-Seong Kim, Yuhwan Ro, YeonGon Cho, Jin Hyun Kim, JoonHo Song, Jaehoon Yu, Seungwon Lee, Jeonghyeon Cho, Kyomin Sohn
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AMD Next Generation "Zen 4" Core and 4th Gen AMD EPYC™ Server CPUs IEEE Micro (IF 3.6) Pub Date : 2024-03-12 Ravi Bhargava, Kai Troester
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Quantifying CO2 Emission Reduction through Spatial Partitioning in Deep Learning Recommendation System Workloads IEEE Micro (IF 3.6) Pub Date : 2024-03-05 Andrei Bersatti, Euna Kim, Hyesoon Kim
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Special Issue on COOL Chips IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Ryusuke Egawa, Yasutaka Wada
This introduction to the special issue on low-power, high speed chips (COOL chips) discusses state-of-the-art COOL chips and the challenges facing researchers. It introduces four articles exploring different solutions for reducing power consumption and enhancing chip performance.
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Computing With COOL Chips IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Hsien-Hsin S. Lee
In this issue, IEEE MICRO welcomes the newly inaugurated Editor-in-Chief Dr. Hsien-Hsin Sean Lee and introduces the Special Issue on COOL chips for the state-of-the-art in low-power design for computing.
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Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part VIII: Patent Families IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Joshua J. Yi
This article is the next article in the series on the patenting behavior and characteristics of computer architecture companies. This article analyzes the characteristics for patent families.
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After the Gold Rush IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Shane Greenstein
What determines market prospects during and after a commercial gold rush, such as the boom presently taking place in commercial generative AI? Many firms face similar technical challenges and commercial risks, and the resolution of one firm’s challenge correlates with that of another. That provides a way of cataloging risks, and the general prospects of some categories of firms, even though it does
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High-Speed Data Communication With Advanced Networks in Large Language Model Training IEEE Micro (IF 3.6) Pub Date : 2024-01-30 Liuyao Dai, Hao Qi, Weicong Chen, Xiaoyi Lu
Large language models (LLMs) like Generative Pre-trained Transformer, Bidirectional Encoder Representations from Transformers, and T5 are pivotal in natural language processing. Their distributed training is influenced by high-speed interconnects. This article characterizes their training performance across various interconnects and communication protocols: TCP/IP, Internet Protocol over InfiniBand
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High Performance Cooling for Power Electronics Via Electrochemical Additive Manufacturing IEEE Micro (IF 3.6) Pub Date : 2024-01-30 Ian Winfield, Tim Ouradnik, Joseph Madril, Michael Matthews, Guillermo Romero
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Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion IEEE Micro (IF 3.6) Pub Date : 2024-01-26 KyungSoo Lee, Sohyun Kim, Joohee Lee, Donguk Moon, Rakie Kim, Honggyu Kim, Hyeongtak Ji, Yunjeong Mun, Youngpyo Joo
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Advancing TinyMLOps: Robust Model Updates in the Internet of Intelligent Vehicles IEEE Micro (IF 3.6) Pub Date : 2024-01-17 Thommas K. S. Flores, Ivanovitch Silva, Mariana B. Azevedo, Thais de A. de Medeiros, Morsinaldo de A. Medeiros, Daniel G. Costa, Paolo Ferrari, Emiliano Sisinni
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Compression Analysis for BlueField-2/-3 Data Processing Units: Lossy and Lossless Perspectives IEEE Micro (IF 3.6) Pub Date : 2023-12-18 Yuke Li, Arjun Kashyap, Yanfei Guo, Xiaoyi Lu
A data processing unit (DPU) with programmable smart network interface card containing system-on-chip (SoC) cores is now a valuable addition to the host CPU, finding use in high-performance computing (HPC) and data center clusters for its advanced features, notably, a hardware-based data compression engine (C-engine). With the convergence of big data, HPC, and machine learning, data volumes burden
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Comprex: In-Network Compression for Accelerating IoT Analytics at Scale IEEE Micro (IF 3.6) Pub Date : 2023-12-15 Rafael Oliveira, Ada Gavrilovska
To enable the Internet of Things (IoT) to scale at the level of next-generation smart cities and grids, there is a need for a cost-effective infrastructure for hosting IoT analytics applications. Offload and acceleration via smartNICs have been shown to provide benefits to these workloads. However, even with offload, long-term analysis on IoT data still needs to operate on a massive number of device
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A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications IEEE Micro (IF 3.6) Pub Date : 2023-12-05 H. Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigne
Compute-in-memory (CIM) has emerged as an effective technique to address memory access bottlenecks for deep neural networks (DNNs). Augmented/virtual reality (AR/VR) devices require running high-performance DNN inference at tight power budgets, making CIMs ideal candidates for low-power on-device acceleration. While high energy efficiencies have been reported at the CIM macro levels, the energy efficiencies
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Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems IEEE Micro (IF 3.6) Pub Date : 2023-11-28 Tatsuya Kubo, Shinya Takamaeda-Yamazaki
Data confidentiality, integrity, and persistence are essential in secure nonvolatile memory (NVM) systems. However, coupling authenticated memory encryption with security metadata persistence incurs nonnegligible performance overheads. Particularly, the integrity update process for the metadata cache bottlenecks execution performance. In this article, we propose Cachet, a novel integrity verification
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Privacy by Memory Design: Visions and Open Problems IEEE Micro (IF 3.6) Pub Date : 2023-11-28 Jianqing Liu, Na Gong
The threat to data privacy has never been more alarming than it is today. Among existing privacy-enhancing technologies, differential privacy (DP) is widely accepted as the de facto standard for privacy preservation. Yet, the software-based implementation of DP mechanisms is neither friendly for lightweight devices nor secure against side-channel attacks. In this article, we propose a first-of-its-kind
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TinyML but by No Means a Tiny Feat! IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Lizy Kurian John
In this article, the EIC introduces the Special Issue on TinyML and bids farewell to the readers, editors, and staff. A collage with the cover pages of IEEE Micro for the last five years is included.
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Special Issue on TinyML IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Vijay Janapa Reddi, Boris Murmann
This IEEE Micro special issue on tiny machine learning (TinyML) explores cutting-edge research on optimizing machine learning models for highly resource-constrained devices like microcontrollers and embedded systems. The articles cover techniques across the full TinyML stack, including efficient neural network design, on-device learning, model compression, hardware–software co-design, and specialized
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Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part VII: Relationship Between Prosecution Time and Claims IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Joshua J. Yi
A previous article in this series showed that the correlation between the prosecution time and the number of claims was relatively low. This article further analyzes that correlation by examining the effect that patent class has.
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Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Matthew D. Sinclair, Parthasarathy Ranganathan, Gaurang Upasani, Adrian Sampson, David Patterson, Rutwik Jain, Nidhi Parthasarathy, Shaan Shah
2023 marked the fiftieth year of the International Symposium on Computer Architecture (ISCA). As one of the oldest and preeminent computer architecture conferences, ISCA represents a microcosm of the broader community; correspondingly, a 50-year-retrospective offers us a great way to track the impact and evolution of the field. Analyzing the content and impact of all the papers published at ISCA so
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The AI Gold Rush IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Shane Greenstein
The recent frenzy of commercial interest in large language models could be compared to a gold rush. We consider the metaphor and where it illuminates the mechanisms shaping business decisions. If the rush indicates the presence of a large long-term opportunity, then expect the supply chain of equipment and software to develop to support it.
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Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0 IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Debendra Das Sharma, Swadesh Choudhary
The sixth generation of PCIe (PCIe 6.0) specification adopted four-level pulse-amplitude modulation signaling at 64 GT/s for maintaining the same channel reach, cost, and power profile as previous generations. Lightweight forward error correction (FEC), a strong cyclic redundancy check (CRC), and link-level replay mechanisms deliver low latency, high bandwidth efficiency, and high reliability. Compute
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Enabling Artificial Intelligence Supercomputers With Domain-Specific Networks IEEE Micro (IF 3.6) Pub Date : 2023-11-06 Dennis Abts, John Kim
Systems designed for artificial intelligence (AI) training and inference exhibit characteristics of both capacity and capability systems that require both tight coupling and strong scaling for model parallelism as well as weak scaling for data parallelism in distributed systems. In addition, managing enormous, 100 billion-parameter language models and trillion-token datasets introduces formidable computational
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COOL-NPU: Complementary Online Learning Neural Processing Unit IEEE Micro (IF 3.6) Pub Date : 2023-11-06 Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Jiwon Choi, Donghyeon Han, Hoi-Jun Yoo
The authors propose a complementary online learning neural processing unit (COOL-NPU) to implement a highly accurate and high-energy-efficient online learning system. It reduces the energy consumption by combining the training methods of convolutional neural network (CNN) and spiking neural network (SNN) and eliminates the power overhead due to the redundant weight update by training trigger with SNN
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A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing IEEE Micro (IF 3.6) Pub Date : 2023-11-03 Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo
A low-power artificial intelligence (AI)-based 3-D rendering processor is proposed for metaverse solutions in mobile platforms. It suggests a brain-inspired rendering acceleration architecture designed with a visual perception core. It removes useless computations by realizing 1) spatial attention, 2) temporal familiarity, and 3) top-down attention. The remaining deep neural network (DNN) inference