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Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-22 Ashish Ranjan Shadangi, Suvra Sekhar Das, Indrajit Chakrabarti
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Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-22 Le Wu, Liji Wu, Xiangmin Zhang, Munkhbaatar Chinbat
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Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-17 Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu
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Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-15 Alireza Nahvy, Zainalabedin Navabi
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FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-12 Md Rafid Muttaki, Md Habibur Rahman, Akshay Kulkarni, Mark Tehranipoor, Farimah Farahmandi
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MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-10 Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li
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Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-10 Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty
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A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-09 Nunzio Spina, Marcello Raimondi, Alessandro Castorina, Egidio Ragonese, Giuseppe Palmisano
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Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-09 Yerzhan Mustafa, Selçuk Köse
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A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-05 Luchang He, Chenchen Xie, Zhao Han, Qingyu Wu, Houpeng Chen, Shibing Long, Xi Li, Zhitang Song
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A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-05 Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song
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Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-02 Bingbing Ma, Wei Li, Hongtao Xu
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A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-04-02 Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Heng Sha, Zunxian Fu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Pengliang Kong, Yunfeng Zhao, Yaoqiang Wang, Weize Yu
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LSM-Based Hotspot Prediction and Hotspot-Aware Routing in NoC-Based Neuromorphic Processor IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-29 Ziyang Kang, Jingwei Zhu, Xun Xiao, Shiming Li, Lei Wang, De Ma, Gang Pan
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FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-25 Amit Mazumder Shuvo, Tao Zhang, Farimah Farahmandi, Mark Tehranipoor
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An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-25 Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
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Proteus: A Pipelined NTT Architecture Generator IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-25 Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
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Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-22 Alexandre Proulx, Jean-Yves Chouinard, Amine Miled, Paul Fortier
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CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-21 Robert Balas, Alessandro Ottaviano, Luca Benini
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-21
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Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-18 Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
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ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency Transformation IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-18 Nastaran Darabi, Maeesha Binte Hashem, Hongyi Pan, Ahmet Cetin, Wilfred Gomes, Amit Ranjan Trivedi
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On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-18 Md Toufiq Hasan Anik, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi
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A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-14 Dongdong Xu, Xiang Wang, Qiang Hao, Jiqing Wang, Shuangjie Cui, Bo Liu
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Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-08 Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
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Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-06 Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli
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Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-05 Daijoon Hyun, Younggwang Jung, Youngsoo Shin
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A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-04 Haoming Zhang, Shuowei Li, Tetsuya Iizuka
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Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-04 Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu
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Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-04 Li Luo, Bochang Li, Lidan Wang, Jinpei Tan, Shukai Duan, Chunxiang Zhu
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Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Bo Zhang, Zeming Cheng, Massoud Pedram
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BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Xin Zheng, Mingjun Cheng, Jiasong Chen, Huaien Gao, Xiaoming Xiong, Shuting Cai
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A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Zhuo Xuan, Shiwei Ren, Chengbo Xue, Guiyu Wang, Xiangnan Li
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A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong
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A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-28 Wei Xiong, Jiacheng Cao, Yaozhang Liu, Jian Wang, Jinmei Lai, Miaoqing Huang
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Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-27 Enlai Li, Sharad Sinha, Wei Zhang
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Rowhammer Vulnerability of DRAMs in 3-D Integration IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-27 Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Tyler Bletsch, Krishnendu Chakrabarty
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-26
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Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-26 Basant Kumar Mohanty
In this article, the combined convolution–lifting scheme is explored to address the design issues of 2-D discrete wavelet transform (DWT) structures. We found that the combined convolution–lifting scheme of type-1 (convolution followed by lifting) is more suitable than convolution or lifting schemes to design 2-D DWT structures with less on-chip memory. Furthermore, the canonic signed digit (CSD)-based
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A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-26 Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
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Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-19 Irith Pomeranz
The fabrication processes of chips in state-of-the-art technologies may introduce defects of various types, and a large number of tests may be needed for fault detection. However, constraints on the storage requirements of a test set can limit the number of tests and, consequently, the fault coverage. It was shown earlier that reductions in the input storage requirements of a test set can be achieved
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A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-16 Changmin Song, Hoyong Jung, Kyoungseop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang
A receiver bridge chip, which supports both the C-PHY version 1.1 and D-PHY version 2.0 specifications of the mobile industry processor interface (MIPI), is proposed to be used in a field-programmable gate array (FPGA)-based frame grabber supporting the MIPI camera serial interface (CSI)-2. The proposed receiver bridge chip consists of a 4-lane D-PHY receiver (RX), a 3-lane C-PHY RX, a digital logic
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Reliable Hardware Watermarks for Deep Learning Systems IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-09 Joseph Franklin Clements, Yingjie Lao
Recent successes in deep learning have indicated that hardware technologies will play a prominent role in future deep learning industries and applications. In light of their value, researchers have recognized that deep neural networks (DNNs) and other deep learning intellectual properties (IPs) can be easily pirated, especially in undefended settings. While multiple avenues of defending deep learning
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Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-09 Musha Ji’e, Hongxin Peng, Shukai Duan, Lidan Wang, Fengqing Zhang, Dengwei Yan
Although multiscroll attractors in dissipative chaotic systems (DCSs) have complex properties, they may be subject to reconstruction attacks in the field of information security. Conservative chaotic systems (CCSs) have no attractors and can effectively resist this danger. To obtain grid-scroll conservative chaotic flows with complex dynamical behaviors, this article proposes a symmetric sine function
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FSpGEMM: A Framework for Accelerating Sparse General Matrix–Matrix Multiplication Using Gustavson’s Algorithm on FPGAs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-02 Erfan Bank Tavakoli, Michael Riera, Masudul Hassan Quraishi, Fengbo Ren
General sparse matrix–matrix multiplication (SpGEMM) is integral to many high-performance computing (HPC) and machine learning applications. However, prior field-programmable gate array (FPGA)-based SpGEMM accelerators either use the inner product algorithm with wasted and costly operations or Gustavson’s algorithm with a cache-based hardware architecture suffering from long-latency cache miss penalties
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Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-02 Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu
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FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in Wireless Time-Varying Channel Environments IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-01 Haoyang Shen, Deepu John, Barry Cardiff
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FLNA: Flexibly Accelerating Feature Learning Networks for Large-Scale Point Clouds With Efficient Dataflow Decoupling IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-30 Dongxu Lyu, Zhenyu Li, Yuzhou Chen, Gang Wang, Weifeng He, Ningyi Xu, Guanghui He
Point cloud-based 3-D perception is poised to become a key workload on various applications. It always leverages a feature learning network (FLN) before backbones to obtain uniform representation from the scattered points. Grid-based FLN (GFLN) that partitions point clouds into uniform grids becomes the main category in recent state-of-the-art (SOTA) works. However, it heavily suffers from significant
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An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-30 Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui Loureiro, Shufan Yang, Hubin Zhao
Due to iterative matrix multiplications or gradient computations, machine learning modules often require a large amount of processing power and memory. As a result, they are often not feasible for use in wearable devices, which have limited processing power and memory. In this study, we propose an ultralow-power and real-time machine learning-based motion artifact detection module for functional near-infrared
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Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-25 Sunwoong Kim, Cameron J. Norris, James I. Oelund, Rob A. Rutenbar
The IEEE 754 standard for floating-point (FP) arithmetic is widely used for real numbers. Recently, a variant called posit was proposed to improve the precision around 1 and −1. Since FP multiplication requires high computational complexity, various algorithmic approaches and hardware accelerator solutions have been explored. In this context, this article proposes a novel area-efficient logarithmic
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A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-25 Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu
A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm2. For a 16 Gb/s PRBS of 27–1, the power of the CDR
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-22
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ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-22 Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu
The homomorphic encryption over the torus (TFHE) is a promising fully homomorphic encryption (FHE) scheme that allows arbitrary homomorphic computations with the programmable bootstrapping (PBS) algorithm. However, PBS suffers from prohibitive computation complexity and latency, which hinders the practical applications of TFHE. To address these challenges, we propose ALT, a field-programmable gate
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A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-16 Xiaoxiao Zheng, Mao Ye, Zhiwei Li, Yao Li, Qiuwei Wang, Yiqiang Zhao
This article presents a low noise and wide linear dynamic 20-channel analog front-end (AFE) array for frequency-modulated continuous-wave (FMCW) light detection and ranging (LiDAR) system. Each channel of the AFE array mainly consists of a shunt feedback transimpedance amplifier (SF-TIA) with a dc cancellation loop (DCL), a post amplifier, and an output buffer. The DCL is proposed to eliminate the