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Careful Seeding for k-Medois Clustering with Incremental k-Means++ Initialization J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-13 Difei Cheng, Yunfeng Zhang, Ruinan Jin
K-medoids clustering is a popular variant of k-means clustering and widely used in pattern recognition and machine learning. A main drawback of k-medoids clustering is that an improper initialization can cause it to get trapped in local optima. An improved k-medoids clustering algorithm, called INCKM algorithm, which is the first to apply incremental initialization to k-medoids clustering, was recently
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A Low-Power Tunable Differentiator Using Voltage Difference Transconductance Amplifier (VDTA) for Tunable PD Controller J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-13 Santosh Routu, Satish Chandra, M. Shanmukha Priya, Pankaj Kumar
The electronically tunable differentiator using a voltage difference transconductance amplifier (VDTA) is proposed, designed, and analyzed. The simulation was done using the Cadence Virtuoso tool of 45nm CMOS technology with a supply voltage of ±0.9V. The maximum power consumption of the proposed circuit is 246μW with a total harmonic distortion of 5.4%. The output can be tuned using four parameters:
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Design and Implementation of Electronically Controllable Sinusoidal Oscillators Using Commercially Available Current-Feedback Operational Amplifiers with Externally Accessible Compensation Node z J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-13 Ivaylo Pandiev
This paper presents the structure and operational principles of high-frequency electronically controllable sinusoidal oscillators employing current-feedback operational amplifiers (CFOAs) with externally accessible compensation node z as active components. The resonant circuits in the oscillators are connected to the terminal z, and for them in the selective network varactor diodes or varicaps as the
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Secure Virtual Machine Migration and Host Overload Detection Using Modified Pelican Optimization with Variable Load Mean Function J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-13 S. Parthasarathy
Low-resource utilization and high-energy consumption have become progressively protuberant issues in cloud data centers. Virtual Machine (VM) migration is the key objective to resolve this issue. Moreover, extreme VM migration might empower Service-Level Agreement (SLA) violations. Few works are considered for optimizing throughput and energy consumption. An efficient VM migration must consider different
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A 12-Bit 1.2-GS/s Current-Steering DAC in 45-NM CMOS Technology J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-13 Tarun Gupta, Sonalika Bhandari, Sachin Taran, Rahul Kumar Gupta
This research paper presents a 12-bit 8–4-segmented current-steering DAC (digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and an efficient digital input bit segmentation. These features contribute
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High-Speed Power Allocation in NOMA System Using FPGA-Based DNN J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-11 Rama Muni Reddy Yanamala, Muralidhar Pullakandam
Artificial Intelligence (AI) is rapidly transforming the healthcare, finance and transportation industries. This paper presents a field-programmable gate array (FPGA)-based neural network accelerator (NNA) design for power allocation in downlink nonorthogonal multiple access (NOMA) networks. The proposed hardware accelerator effectively cuts computational costs while delivering performance on par with
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Saliency-Guided Sparse Low-Rank Tensor Approximation for Unsupervised Anomaly Detection of Hyperspectral Remote Sensing Images J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-10 ZhiGuo Du, Lian Yang, MingXuan Tang
Hyperspectral anomaly detection can separate sparse anomalies from the low-rank background component under an unsupervised behavior due to sufficient spectral information. Therefore, hyperspectral image anomaly detection technology has great application potential and value in public security and national defense. Currently, most existing models attempt to detect anomalous targets with a sparsity prior
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FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-10 Mitul Sudhirkumar Nagar, Sohan H. Patel, Pinalkumar Engineer
Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures
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FinFET-Based Low-Power Improved PDP 4:2 Approximate Compressor Design J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-10 Shams Ul Haq, Vijay Kumar Sharma
In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion
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Evaluation of the Signal and Noise of Readout Electronics for Radiation Detector by Using MATLAB Simulation Program J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-10 Jamal Assaf, Zuheir Ahmad, Kamal Skeiker
Within the frame of this work, a user-friendly MATLAB program for the simulation of signals and electronic noise at the nuclear radiation readout system was developed. Signal and noise in terms of equivalent noise charge (ENC) have been evaluated. Five noise sources were considered in order to have high simulation accuracy. The role and influence of different parameters of the readout circuits on the
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Research on Effective Wind Speed Estimation and Prediction Method Based on Wind Turbine Driven Pumping Unit J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-09 Haixia Niu, Chunyou Zhang, Xiaolong Gao, Xinfeng Lu, Xue Rui
This paper takes the wind turbine of the new energy pumping unit as the study subject, which mainly analyzes realistic wind speed estimation on the windward side of the wind turbine and then proposes a wind turbine speed control method based on wind speed estimation. The support vector regression (SVR) model is built first in this study, and the parameters of the SVR model are optimized by the particle
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A Defects Classification Algorithm for the Hybrid OBT–IDDQ Fault Diagnosis Technique in Analog CMOS Integrated Circuits J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-04 Dejan D. Mirkovic, Milena J. Stanojlovic Mirkovic, Miljana L. J. Milic, Vladimir Z. Petrovic
In this paper, a robust fault detection methodology for complex analog CMOS integrated filters is presented. It is based on combining the two types of testing methodologies, Oscillation-Based Testing (OBT) and IDDQ testing, i.e., measuring of the power-supply current (IDD). The proposed methodology is applied to the Bi-quad Sallen–Key band-pass (BP) filter cell with relatively complex, two-stage, class-AB-output
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A Deep Neural Network-Based Intelligent Forecasting Approach for Multi-Dimensional Economic Indexes in Smart Cities J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-04 Zhuo Chen, Wei Peng, Xuesong Yao
Intelligent forecasting of economic indexes has been an important demand for sustainable management of smart cities. Existing methods for this purpose were mostly established upon the basis of economic mechanism. Econometric models are the most general technical means in this area. However, in era of digital economy, increasing amount of big data has brought great change to traditional production.
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Distributed Event-Triggered Algorithm with Network Independent Step-Size for Constraint-Coupled Optimization Problems J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-04 Baitong Chen, Jianhua Yang, Wei Lu, W. Pedrycz, Changhai Sun
In this study, we introduce a distributed algorithm that is specifically designed to address optimization problems featuring a decomposable objective function and equality constraints. To minimize the amount of communication required, we incorporate an event-triggered mechanism that enables information exchange only when variable values exceed predefined thresholds. Importantly, our proposed algorithm
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A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-04 Sahar Doolabi, Mehdi Taghizadeh, Mohammad Hossein Fatehi, Jasem Jamali
This paper presents an innovative general structure for a single-loop Sigma-Delta (ΣΔ) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the
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Deep Fusion Module for Video Action Recognition J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-03 Yunyao Li, Zihao Zheng, Mingliang Zhou, Guangchao Yang, Xuekai Wei, Huayan Pu, Jun Luo
In video action recognition, effective spatiotemporal modeling is crucial. However, traditional two-stream methods face challenges in integrating spatial information from RGB images and temporary information from optical flow without long-range temporal modelling. To address these limitations, we propose the Deep Fusion Module (DFM), which focuses on the deep fusion of spatial and temporal information
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A Fuzzy Neural Network-Based Intelligent Warning Method for Financial Risk of Enterprises J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-04-03 Qing Yao, Chunmei Mao, Yundong Guo
The fast warning for financial risk of enterprises has always been a realistic demand for their managers. Currently, this mainly relies on expert experience to make comprehensive analysis from massive business data. Benefitting from the strong computational performance of deep learning, this paper proposes a fuzzy neural network (FNN)-based intelligent warning method for financial risk of enterprises
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Hardware Prefetching Tuning Method Based on Program Phase Behavior J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-28 Liangming Huang, Li Yan, Tiebin Wu
Modern high-performance processor systems universally employ hardware prefetch engines to address the “memory wall” issue. Nonetheless, prefetchers are typically activated with the default configuration at system startup, and this fixed configuration does not always achieve the intended performance in the face of varied programs and may even degrade performance. As a result, it is crucial to investigate
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A Data-Driven Autonomous Assessment Framework for Education Quality Based on Multiscale Deep Learning J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-28 Junqiao Wang, Sung-Je Cho, Xiwang Chen
Nowadays, computational intelligence-assisted autonomous assessment of education quality has become a more and more general concern in the area of smart education management. As education quality assessment is a complicated process with multiple heterogeneous factors, it remains challenging to make effective assessment using simple information modality and criteria. To deal with this issue, this paper
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SPC-Indexed Indirect Branch Hardware Cache Redirecting Technique in Binary Translation J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-28 Chunqiang Li, Zhiwei Liu, Yunhai Shang, Lenian He, Xiaolang Yan
In the domain of process virtual machine (PVM) binary translation, the difference in address space layout between the guest program and the translated program requires the recalculation of jump instruction targets, resulting in suboptimal execution efficiency. This paper presents a novel method called SPC-Indexed Indirect Branch Hardware Cache Redirecting (SPCIC) technique. SPCIC utilizes specialized
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Analysis and Simulation of Current Balancer Circuit for Phase-Gain Correction of Unbalanced Differential Signals J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-28 Zainab Baharvand, Abdolreza Nabavi, Habibollah Zolfkhani
The phase and gain imbalance of a balun output can be adjusted by a differential current balancer (DCB) circuit. The performance of DCB circuit, for correcting the phase (gain) imbalance, is analyzed for a wide range of input signal level, and the accuracy is verified with circuit simulation. To illustrate the phase-error/gain-error (PE/GE) correction, a 30–40GHz DCB circuit is designed and simulated
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Power Attack Vulnerability Assessment of Circuit-Level PRESENT Encryption IP Using Artificial Intelligence Mechanisms J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-28 Kailash Natarajan, R Sricharan, M Thriambak, Anjana Jyothi Banu, A Prathiba, V S Kanchana Bhaaskaran
Artificial Intelligence (AI) schemes eliminate the need for intellectual human knowledge of crypto algorithms to facilitate side-channel attacks on security implementations. Side channel attack analysis for circuit-level hardware (VLSI) implementations of symmetric-key block ciphers through artificial machine models are yet to be addressed. The proposed design of block cipher architecture, which is
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Image Classification Method Based on Multi-Scale Convolutional Neural Network J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-27 Shaobo Du, Jing Li
Traditional convolutional neural networks (CNNs) typically use fixed scale convolutional kernels for feature extraction when processing image classification tasks, while ignoring the multi-scale information present in the image. To overcome this limitation, we propose an algorithm based on multi-scale CNNs, which capture features at different levels by introducing convolutional kernels of different
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AWLC: Adaptive Weighted Loop Closure for SLAM with Multi-Modal Sensor Fusion J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-27 Guangli Zhou, Fei Huang, Wenbing Liu, Yuxuan Zhang, Hanbing Wei, Xiaoqin Hou
The present prevailing loop closure detection algorithm is mainly applicable for simultaneous localization and mapping (SLAM). Its effectiveness is contingent upon environmental conditions, which can fluctuate due to variations in lighting or the surrounding scenario. Vision-based algorithms, while adept during daylight hours, may falter in nocturnal settings. Conversely, lidar methods hinge on the
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A Low-Power Fully Differential Level-Crossing ADC Based on Single-Reference Comparator for Wireless Medical Implantable Devices J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-26 Behnam Yazdani, Shahin Jafarabadi Ashtiani
This paper introduces a low-power fully differential fixed window level-crossing analog-to-digital converter (LC-ADC) for wireless medical implantable devices. The LC-ADC could be an excellent candidate for low-power systems due to the reduction of sampling points for bio-potential signals. Different from existing fixed window LC-ADCs, which use a 1-bit DAC or scaler and two reference levels to move
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Advanced Authentication and Energy-Efficient Routing Protocol for Wireless Body Area Networks J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-25 Padma Vijetha Dev Bakkaiahgari, K. Venkata Prasad
Recently, wireless body area network (WBAN) becomes a hot research topic in the advanced healthcare system. The WBAN plays a vital role in monitoring the physiological parameters of the human body with sensors. The sensors are small in size, and it has a small-sized battery with limited life. Hence, the energy is limited in the multi-hop routing process. The patient data is collected by the sensor
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Assessment of Power System Stability During Transients Using Deep Residual Shrinkage Network and CBAM Integration J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-25 Qiang Wang, Zifan Nie, Hongwei Liu
Aiming at the noise that may exist in the data collection and transmission of power system synchronous phasor measurement unit (PMU), as well as the imbalance between stable and unstable samples, making the model likely to tilt to most kinds of samples, thus affecting the evaluation results of power system transient stability model, a transient stability assessment method integrating Convolutional
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Power Quality (PQ) Analyses of DG Utilizing Unified Power Quality Conditioner (UPQC) by White Shark Optimizer and Recalling-Enhanced Recurrent Neural Network J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-21 Chapala Shravani, R. L Narasimham2, G Tulasi Ram Das3
This paper proposes a novel hybrid technique for enhancing power quality (PQ) in distributed generation (DG) systems by deploying a unified power quality conditioner (UPQC). Here, the proposed hybrid method is the joint execution of white shark optimizer (WSO) and recalling-enhanced recurrent neural network (RERNN), called the WSO-RERNN technique. The primary objective of this novel approach is to
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Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-18 Kuntal Chakraborty, Alak Majumder, Abir J Mondal
This work suggests an all-digital temperature sensor with a high sampling rate that is based on a time-to-digital converter (TDC). Two on-chip voltage-controlled oscillators (VCOs) are used in the design of the sensor core, which senses temperatures between −40∘C and 200∘C. For digital code conversion, the outputs of the VCO are fed into two asynchronous counters. In both low- and high- resolution
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CC-CBTA-Based Floating Inductance Simulator with CM/VM PID Controllers J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-16 M. Sagbas, Z. G. Cam Taskiran, U. E. Ayten
This work describes voltage-mode (VM), current-mode (CM) PID controllers and an electrically controllable floating inductance (FI) simulator circuit. Only a single current-controlled current backward transconductance amplifier (CC-CBTA) and a grounded capacitor are used in the proposed FI simulator circuit. One CBTA, one CC-CBTA, two capacitors and one resistor are used in the proposed PID controllers
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A Deep Vision Sensing-Based Smart Control Method for Apple-Picking Robots Under the Context of Agricultural E-Commerce J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-16 Yang Qiu, Man Yang
The growing development of the agricultural e-commerce industry is promoting the Digital transformation of agricultural production and logistics. Aiming at the problem of labor shortage in apple picking, this paper proposes a performance control method for robot apple picking based on a nonlinear wide convolutional neural network (NLWCNN) and multi-objective cooperative distance transformation algorithm
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ASIC Design of Low Power Sobel Edge Detection Filter: An Analog Approach J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-16 K. N. Vijeykumar, Silambarasan Dharmalingam, Vineel Talluri Jessy, V. Aravind
This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 ×3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical
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Leveraging Variable Density Honeycomb Structures for Innovative Design in Mission-Critical Embedded Devices J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-16 Xi Yan, Song Pang, Naixun Zhou, Bowen Pang, Bei Peng, Zhi Zeng
The imperative for lightweighting technologies, paramount in mission-critical cyber-physical systems (CPSs) including aerospace, automotive and allied sectors, hinges upon optimizing energy efficiency and curbing product weight. Honeycomb structures, celebrated for their exceptional strength-to-weight ratio, have indisputably guided the pursuit of lightweight design. This paper expounds upon the versatility
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Experimental and Theoretical Analysis of Bispectrum Characteristics of Phase Coupled Signals J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-16 Wenbing Wu, Xiaojian Yuan
Fourier transform points out that a certain function that meets certain conditions can be decomposed into a linear combination of trigonometric functions (sine or cosine functions). The functions of high-order cumulant include suppressing the Gaussian noise, eliminating independent signal components, and identifying the phase coupling phenomenon of the signal. To prove this hypothesis, this study constructs
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Review on High-Speed Dynamic Comparators for Analog to Digital Converters J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-14 Komala Krishna, Nandakumar Nambath
This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator
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Dual-Notched UWB Orthogonal MIMO Antenna with Improved Gain Characteristics Using Frequency Selective Surfaces for Wireless Communication Applications J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-14 Yalavarthi Usha Devi, Boddapati Taraka Phani Madhav, Sudipta Das, Tanvir Islam, Mohammed El Ghzaoui
In this paper, a complementary split ring resonator (CSRR) loaded compact CPW-fed circular shaped monopole UWB antenna with dual band notch characteristics is designed on an FR-4 substrate. The propounded band-notched UWB antenna is integrated with two frequency selective surface layers referred as bandpass frequency selective surface (FSS-1) and reflector (FSS-2) to offer enhanced radiation performance
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A Proactive Self-Adaptation Approach Based on Ensemble Prediction for Service-Based Systems J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-14 Shenglong Xie, Lu Wang, Qingshan Li, Xiangtian Guo
Service-based systems (SBSs) are a unique category of software systems that dynamically combine various third-party services at runtime to deliver complex and adaptive functionality. This dynamic composition introduces a high level of unpredictability and uncertainty, creating potential anomalies and exerting significant pressure on system maintenance. To tackle this challenge, the conventional approach
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A Deep Neural Network-Fused Mathematical Modeling Approach for Reliable Flight Control of Small Unmanned Aerial Vehicles J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-14 Gang Xu, Weibin Su, Mingbo Pan, Yikai Wang, Zhengfang He, Jiarui Dong, Jiangzheng Zhao
In order to ensure the flight safety of small unmanned aerial vehicles (UAVs), a deep neural network-fused mathematical modeling approach is put up for reliable flight control of small UAVs. First, engine torque, thrust eccentricity and initial stop angle are taken into full consideration. A six-degree-of-freedom nonlinear model is formulated for small UAVs, concerning both ground taxiing and air flight
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Development of CPW Fed Slot Antenna with CSRR for Biomedical Applications J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-14 Koteswararao Seelam, S. V. Rama Rao, Srinivasa Rao Kandula, Abdul Hussain Sharief, Venkata Reddy Adama, S. Ashok Kumar
This paper presents a complementary split-ring resonator (CSRR) loaded coplanar waveguide (CPW) fed with a circular shape, miniaturized diamond slot planar monopole antenna. The proposed antenna for healthcare monitoring biomedical applications uses the industrial medical and scientific band. The antenna design and development to implant the human phantom are proposed. The primary goal of this work
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Impact of Variability on Novel Transistor Configurations in Adder Circuits at 7nm FinFET Technology J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-13 Umayia Mushtaq, Md. Waseem Akram, Dinesh Prasad, Aminul Islam, Bal Chand Nagar
This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7nm technology node is analyzed with respect to its
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A Radial Basis Function Neural Network-Based Fast Forecasting Model for Regional Economy J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-11 Tangfa Liu, Yan Li, Jianfeng Jiang
The computational intelligence-based digital forecasting for social systems has been a novel tendency. This work takes forecasting of regional economy as the problem scenario, and introduces radial basis function neural network (RBFNN) to deal with this concern. Hence, an RBFNN-based fast forecasting model for regional economy is constructed in this paper. First, the economic flow data are encoded
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Robust Object Detection Using Fire Hawks Optimizer with Deep Learning Model for Video Surveillance J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-11 S. Prabu, J. M. Gnanasekar
In recent years, video surveillance has become an integral part of computer vision research, addressing a variety of challenges in security, memory management and content extraction from video sequences. This paper introduces the Robust Object Detection using Fire Hawks Optimizer with Deep Learning (ROD-FHODL) technique, a novel approach designed specifically for video surveillance applications. Combining
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A Novel Lightweight NIDS Framework for Detecting Anomalous Data Traffic in Contemporary Networks J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-11 Yogendra Kumar, Vijay Kumar, Basant Subba
Network Intrusion Detection Systems (NIDSs) have been proposed in the literature as security tools for detecting anomalous and intrusive network data traffic. However, the existing NIDS frameworks are computation-intensive, thereby making them unsuitable for deployment in resource-constrained networks with limited computational capabilities. This paper aims to address this issue by proposing computationally
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Design, Simulation and Comparative Analysis of Two Stage Operational Amplifier Based on CNTFETs Using Indirect Feedback Frequency Compensation J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-09 Mir Bintul Islam, M. Nizamuddin, S. S. Islam
In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid
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Machine Learning Based Open Switch Fault Detection and Localization of Inverters J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-06 V. Rinsha, Vivek Kumar Sharma, Nithin Raj, G. Jagadanand
The location and detection of switch faults is a crucial step in improving the dependability of inverters, which is a requirement for critical applications. This paper focuses on a machine learning-based approach for the open-switch fault detection system for cascaded H-bridge (CHB) multilevel inverters (MLI) used in high- and medium-power applications. Each switch failure is taken into account in
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Digital Background Calibration Assisted with Noise-Shaping for a 10-b Bridged SAR ADC J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-05 Shuang Xie, Yong Wang
This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected
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Non-Isolated High Gain Interleaved DC–DC Converter with Voltage Multiplier and Switched Capacitor for Renewable Energy Systems J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-05 R. Subbulakshmy, R. Palanisamy
A novel non-isolated high-gain DC–DC converter for green energy employment is presented and analyzed. The proposed converter comprises a switched capacitor cell, passive clamp circuit, coupled inductors, and voltage multiplier unit. An interleaved boost converter (IBC) is placed on the input side of the proposed design. The voltage multiplier unit (VMU) with the secondary windings of the coupled inductors
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Real-Time Early Warning Method of Distribution Transformer Load Considering Meteorological Factor Data J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-02 Shan Li, Wei Huang, Yangjun Zhou, Xin Lu, Zhiyang Yao
The traditional real-time load warning method for distribution transformers has problems such as low recall rate, low warning accuracy, and long warning time, which may lead to potential equipment failures or overload situations not being detected and dealt with in a timely manner, increasing the safety risk of transformer operation and potentially causing safety issues such as equipment damage, fire
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A Convolutional Neural Network Image Compression Algorithm for UAVs J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-03-02 Yongdong Dai, Jing Tan, Maofei Wang, Chengling Jiang, Mingjiang Li
In the task of power line inspection, Unmanned Aerial Vehicles (UAVs) are frequently used for capturing images. With the rapid advancement of sensor technology, the spatial, radiometric, and spectral resolutions of UAV images are constantly improving, leading to an increased storage requirement for individual images. Given that UAVs usually operate with limited computational resources, transmission
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Task Scheduling Optimization for UAV Electrical Image Fault Detection with Wireless Power Transfer J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-29 Renshu Wang, Wenbin Wu, Zhiwei Fu, Bojian Chen, Xiaojie Wu
The smooth operation of the power system is of significant importance for ensuring societal stability. Therefore, regular inspections of the power system are necessary. The most efficient method for power inspection is to utilize Unmanned Aerial Vehicles (UAVs) to assist inspection. However, the UAV inspection still needs human resources to operate and manage the UAVs effectively. This paper proposes
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Ensemble Model for Stock Price Forecasting: MapReduce Framework for Big Data Handling: An Optimal Trained Hybrid Model for Classification J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-29 R. Senthamil Selvi, V. Sankari, N. Ramya, M. Selvi
A number of authors have focused on this study to examine how huge data are perceived. A novel big data classification paradigm is introduced by the work’s preprocessing, feature extraction and classification techniques. Data normalization is carried out at the preprocessing stage. The MapReduce framework is then utilized to manage the massive data. Statistical features (mean, median, min/max and SD)
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A High-Gain Directional 1 × 8 Planar Antenna Array for 2.4GHz RFID Reader Applications J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-28 Abdelaaziz El Ansari, Sudipta Das, Tanvir Islam, Sivaji Asha, Najiba El Amrani El Idrissi, Boddapati Taraka Phani Madhav
This research paper deals with a directional high gain PCB 1×8 antenna array for 2.4ISM band utilizations. To achieve this antenna array, a well-matched equal-split 9dB-power splitter is designed and integrated with the suggested antenna array. It exhibits a wide operating range of 506MHz (2.022–2.528GHz) and splits the feed power to 8 equal-in-phase output quantities. Then eight identical patch elements
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Resistive Switching Property of Euforbia Cotinifolia Plant Extract for Potential Use in Eco-Friendly Memory Devices J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-28 Zolile Wiseman Dlamini, Sreedevi Vallabhapurapu, Srinivasu Vijaya Vallabhapurapu
Resistive switching memory devices based on organic materials are intriguing. These devices are biodegradable and nontoxic to living organisms. In this work, using euphorbia cotinifolia plant extract was investigated for its applicability as an active layer of a resistive switching memory device consisting of silver top electrode and indium-doped tin oxide bottom electrode. This study selected Euphorbia
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Spatial–Spectral Total Variation-Regularized Low-Rank Tensor Representation for Hyperspectral Anomaly Detection J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-28 ZhiGuo Du, Xingyu Chen, Minghao Jia, Xiaoying Qiu, Zelong Chen, Kaiming Zhu
Hyperspectral anomaly detection is a vital aspect of remote sensing as it focuses on identifying pixels with distinct spectral–spatial properties in comparison to their background representations. However, existing methods for anomaly detection in HSIs often overlook the spatial correlation between pixels by converting the three-dimensional tensor data into its folded form of independent signatures
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Cross-Subject Brain–Computer Interfaces with Joint Distribution Alignment J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-28 Xianghong Zhao, Longhua Ma, Weiming Cai, Bin Lian, Jialin Cui, Lingjian Ye
Distributions of electroencephalogram (EEG) data vary greatly across different subjects. It is a very important issue how to generalize models across subjects. In this paper, an algorithm is proposed to build high-performance cross-subject motor-imagery brain–computer interfaces (BCIs) for a new subject. First, a novel distance metric is proposed to quantify the joint distribution discrepancy (JDD)
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Nanotube TFET Biosensor with High-Frequency FOMs as Sensing Parameter J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-22 Anju Gedam, Bibhudendra Acharya, Guru Prasad Mishra
This paper proposes a new dielectrically modulated (DM) twin cavity nanotube biosensor and its sensitivity evaluation suitability by the transit time (τ) and device efficiency (gm/Ids). In addition, the vertical structure of the device also helps the uniform spreading of biomolecules within the nanogap cavity region. The inner cavity of the proposed biosensor offers more space for the stabilization
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Edge Perception Temporal Data Anomaly Detection Method Based on BiLSTM-Attention in Smart City Big Data Environment J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-22 Bin Xia, Jun Zhou, Fanyu Kong, Jiarui Yang, Lin Lin, Xin Wu, Qiong Xie
The improvement of edge perception layer anomaly detection performance has an immeasurable driving effect on the development of smart cities. However, many existing anomaly detection methods often suffer from problems such as ignoring the correlation between multiple source temporal sequences and losing key features of a single temporal sequence. Therefore, a new anomaly detection method using BiLSTM
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A Statistical Model-Based Approach for Reproducing Intermittent Faults in Electrical Connectors under Varying Vibration Loading Conditions J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-22 Xinglong Zhou, Kuntao Ye, Sheng Li, Songhua Liu
The performance of electrical connectors can be significantly impacted by periodic variations in contact resistance caused by vibrational stress. Intermittent faults resulting from such stress are characterized by their random and fleeting nature, making it difficult to study and replicate them. This paper proposes a novel method for reproducing intermittent faults in electrical connectors. To implement
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New Approaches for Realizing Transconductance-boosted VDTA Structures J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-22 Parveen Rani, Priyanka Gupta, Gurumurthy Komanapalli, Rajeshwari Pandey
This paper presents two new transconductance-boosted architectures of the voltage differencing transconductance amplifier (VDTA). The first architecture (VDTA-I) relies on the technique of transconductance enhancement using partial positive feedback which is realized through negative impedance implemented using a cross-coupled amplifier. The second architecture (VDTA-II) incorporates the concept of
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A Biometric Key-Enhanced Multimedia Encryption Algorithm for Social Media Blockchain J. Circuits Syst. Comput. (IF 1.5) Pub Date : 2024-02-22 Tao Liu, Zhongyang Yu
Social media blockchain is emerging as a promising solution to deal with privacy issues, by putting user privacy in edge nodes rather than centralized nodes. Under the protection of information encryption, only those who have cryptographic keys can get access to key information. This work aims at multimedia information in social media blockchain and utilizes the RSA encryption mechanism to construct