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PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-17 Tingran Chen, Wenjia Wang, Jiaqi Chen, Haotian Fu, Wente Yi, Bojun Cheng, He Zhang, Biao Pan
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A 0.35mm$^2$ 94.25$\upmu$W Fully Integrated NFC Tag IC Using 0.13$\upmu$m CMOS Process IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-17 De-Ming Wang, De-Zhi Li, Jing Wu, Jian-Hao Cai, Qing-Hua Zhong, Xin Huang, Jian-Guo Hu
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AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-17 Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar
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Optimization of Quantum Circuits for Stabilizer Codes IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-17 Arijit Mondal, Keshab K. Parhi
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DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-15 Yufei Ma, Yikan Qiu, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang
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Resilient Synchronization for Insecure Markovian Jump Neural Networks to Mitigate Dual Cyber Attacks IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-15 Xiaohang Li, Peng Shi, Weidong Zhang, Mehrdad Saif
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Efficient and Side-Channel Resistant Ed25519 on ARM Cortex-M4 IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-15 Daniel Owens, Rabih El Khatib, Mojtaba Bisheh-Niasar, Reza Azarderakhsh, Mehran Mozaffari Kermani
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Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-11 Hwaseong Shin, Seokjae Song, Hyunji Jeong, Quanzhen Duan, Jeongjin Roh
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A Compact Dickson Hybrid Boost Converter With 5-mV Input 90.5% Peak Efficiency and On-Chip Cold-Start for Thermoelectric Energy Harvesting IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-11 Chenkang Xue, Ruijie Xi, Huipeng Xu, Lijie Shao, Xu Yang, Yong Ding, Wuhua Li, Wanyuan Qu
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Theory and Low-Power Design of Moving Accumulative Sign Filter IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-11 Yingjun Xia, Jianjiang Luo, Peng Yin, Dengwei Yan, Xichuan Zhou, Amine Bermak, Fang Tang
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Quantification of Cascading Failure Propagation in Power Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-11 Meixuan Jade Li, Chi K. Tse
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Frequency-Transformation-Based Co-Designed Lowpass-Single$/$Multi-Passband-Highpass RF Filters IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-08 Roberto Gómez-García, Li Yang, Mohamed Malki, José-María Muñoz-Ferreras
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In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-08 Steven Davis, Jianbo Liu, Boyang Cheng, Muya Chang, Ningyuan Cao
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Dynamic Event-Triggered Byzantine-Resilient Output Regulation in Continuous-Time High-Order Multiagent Systems With Static/Dynamic Leader IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-08 Chenhang Yan, Liping Yan, Yuezu Lv, Yuanqing Xia
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In Situ Wide-Range Permittivity Measurement: Compact, Cost-Effective, and Highly Sensitive Sensor Using Reconfigurable Phase Shifter IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-08 Rasool Keshavarz, Nastouh Nikkhah, Negin Shariati
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Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-08 Xin Chen, Yuxin Bai, Hao Cai, Congyi Zhu, Xinjie Zhou, Ying Zhang, Weiqiang Liu
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Impact of Aging and Process Variability on SRAM-Based In-Memory Computing Architectures IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-05 Jani Babu Shaik, Xinfei Guo, Sonal Singhal
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Self-Shielded Single-and Dual-Band Quad-Mode Substrate Integrated Waveguide Bandpass Filters Based on Mixed-Mode Cavity IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-05 Qing Liu, Lin-Sheng Wu, Dong-Fang Zhou, Ke Gong, De-Wei Zhang
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Two-Dimensional Discrete Bi-Neuron Hopfield Neural Network With Polyhedral Hyperchaos IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-05 Bocheng Bao, Haigang Tang, Yuanhui Su, Han Bao, Mo Chen, Quan Xu
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Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-03 Hao Xu, Shujiang Ji, Yizhuo Wang, Xinyi Lin, Hao Min, Na Yan
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Stabilization of Noisy Sampled-Data Networked Control Systems: Application to Interleaved Flyback Modular Integrated Converter Circuit IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-04-01 Tianjiao Liu, Jianwei Xia, Guoliang Chen, Ju H. Park, Xiangpeng Xie
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IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-28
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Introducing IEEE Collabratec IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-28
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Multi-Valued Model for Generating Complex Chaos and Fractals IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-28 Yinxing Zhang, Zhongyun Hua, Han Bao, Hejiao Huang
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IEEE Circuits and Systems Society Information IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-28
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IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-28
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The Charge Non-Conservation Paradox Implied by Loss Free Resistors IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-27 Ivo Barbi, Sigmund Singer
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Current Zero-Crossing Shift During Compensation of Dead-Time Distortion in PWM VSI and Its Corrective Action in Current Sensor-Less Compensation IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-27 Dipankar Chatterjee, Kaushik Mukherjee, Chandan Chakraborty, Suvarun Dalapati
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Distributed Non-Cooperative Games and Distributed Learning in Linear and Nonlinear Systems: An Overview IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-26 Fuxiao Tan, Kuankuan Qi
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Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-26 Ying Liu, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang, Ru Huang, Le Ye, Yufei Ma
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Fuzzy-Based Bipartite Quasi-Synchronization of Fractional-Order Heterogeneous Reaction-Diffusion Neural Networks via Intermittent Control IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-26 Yao Xu, Zhuozhen Jiang, Xiangpeng Xie, Wenxue Li, Yongbao Wu
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A Fully Integrated Stimulator With High Stimulation Voltage Compliance Using Dynamic Bulk Biasing Technique in a Bulk CMOS Technology IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-25 Yixin Zhou, Keping Wang, Simeng Yin, Wen-Yuan Li, Fanyi Meng, Zhi-Gong Wang, Kaixue Ma
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Lumped-Distributed Resonators Providing Multiple Transmission Zeros in Bandpass Filters With Simple and Mixed Couplings IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-25 Alexander V. Zakharov, Sergii M. Litvintsev
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Efficiency Enhancement Technique for Outphasing Amplifier With Extended Power Back-Off Range IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-25 Weiwei Wang, Shichang Chen, Yixi Tang, Jialin Cai, Giovanni Crupi, Quan Xue
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DRGA-Based Second-Order Block Arnoldi Method for Model Order Reduction of MIMO RCS Circuits IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-25 Hai-Bao Chen, Xinjie Zhang, Wenjie Zhu, Jie Chen, Pengpeng Ren, Zhigang Ji, Junhua Liu, Runsheng Wang, Ru Huang
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Neural Network Based Iterative Learning Control for Dynamic Hysteresis and Uncertainties in Magnetic Shape Memory Alloy Actuator IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-22 Miaolei Zhou, Liangcai Su, Chen Zhang, Luming Liu, Yewei Yu, Xiuyu Zhang, Chun-Yi Su
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Consensus Tracking of Switched Heterogeneous Nonlinear Systems With Uncertain Target IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-21 Yaping Sun, Xinsong Yang, Peng Shi, Housheng Su
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VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-21 Elivander Judas Tadeu Pereira, Dayan Adionel Guimarães, Rahul Shrestha
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An RF Modulation Based on $k$-th Order PWM Harmonic IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-21 Juan I. Morales, Fernando Chierchie, Pablo S. Mandolesi, Eduardo E. Paolini
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Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-21 Jinn-Shyan Wang, Pei-Yuan Chou
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Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-21 Zhuo Chen, Kezhu Song, Dongwei Zou, Chengyang Zhu, Yuecheng Xu
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A Compact DC-DC Converter With Pulse-Counting MPPT and Fast One-Path Self-Startup for Thermal Energy Harvesting IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-21 Seong-Yeon Moon, Seneke Chamith Chandrarathna, Arooba Shafique, Jong-Wook Lee
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Differential Flatness of Single-Input Commensurate Delay Systems With Applications to Trajectory Planning, Tracking, and Transformation to Fully Actuated Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-20 Zhao-Yan Li, Yu Liu, Bin Zhou
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A 69MHz-Bandwidth 40$V/\mu$s-Slew-Rate 3n$V/\surd{Hz}$-Noise 4.5$\mu$V-Offset Chopper Operational Amplifier IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-20 Yarallah Koolivand, Yasser Rezaeiyan, Milad Zamani, Meysam Akbari, Omid Shoaei, Kea-Tiong Tang, Farshad Moradi
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A Fully Integrated 1 GHz 8A I$_{\mathrm{max}}$ Step-Down and Step-Up Switched Capacitor Voltage Regulator in 3 nm FinFET Technology Featuring Auto Mode Transition IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-20 Arvind Raghavan, Keng Chen, Huanhuan Zhang, Sivaraman Masilamani, Tamir Salus, Rachid Rayess, Gayathri Devi Sridharan, Aruna Payala, Jianrong Chen
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Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-18 Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai
The limitations of traditional von Neumann architectures and digital computing are the bottlenecks for high-speed signal processing capabilities, not to mention the explosion of information growth. To tackle this challenge, this paper proposes an artificial neural network (ANN) equalizer based on the memristor for high-speed channel transmission at 112Gbps with 4-level pulse amplitude modulation (PAM4)
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Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-18 Donghyeon Yi, Seoyoung Lee, Injun Choi, Gichan Yun, Edward Jongyoon Choi, Jonghee Park, Jonghoon Kwak, Sung-Joon Jang, Sohmyung Ha, Ik-Joon Chang, Minkyu Je
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Expectation-Maximization Based Disturbance Identification and Velocity Tracking for Gimbal Servo Systems With Dynamic Imbalance IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-14 Xiaoyu Guo, Wenshuo Li, Yangyang Cui, Chenliang Wang, Zhengtao Ding
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Approximate Belief-Selective Propagation Detector for Massive MIMO Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-14 Wenyue Zhou, Zhenhao Ji, Zeqiong Tan, Zhuangzhuang You, Xiaosi Tan, Xiaohu You, Chuan Zhang
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A 3.0$\mu$Vrms, 2.4 ppm/$^{\circ}$C BGR With Feedback Coefficient Enhancement and Bowl-Shaped Curvature Compensation IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-14 Xufeng Liao, Yuxiang Zhang, Shaohua Zhang, Lianxi Liu
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A 0.5–2.5 GHz Mixer First Receiver With 200 MHz RF Bandwidth and $+$18.5 dBm OB-IIP3 in 180 nm CMOS for 5G NR Band IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-13 Anupam Kumari, Darshak Bhatt
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$H_{\infty}$ State Estimation for Two-Time-Scale Markov Jump Complex Networks Under Analog Fading Channels: A Hidden-Markov-Model-Based Method IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-12 Feng Li, Youzhi Cai, Lei Su, Hao Shen, Shengyuan Xu
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Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-12 Yichun Li, Shuping Ma, Xiaotai Wu, Yang Tang
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A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-11 Paolo Melillo, Simone Zaffin, Mauro Leoncini, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
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110–170 GHz On-Chip Calibration Using Deep Neural Networks IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-11 Haowen Cai, Sanming Hu, Xinge Huang, Yizhu Shen
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Observerless Output Feedback Control of DC-DC Converters Feeding a Class of Unknown Nonlinear Loads via Power Shaping IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-08 Wei He, Yanqin Zhang, Wangping Zhou
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A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-08 Yuqing Ren, Hassan Harb, Yifei Shen, Alexios Balatsoukas-Stimming, Andreas Burg
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A 0.14-nJ/b 200-Mb/s 2.7–3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-07 Bowen Wang, Cong Ding, Yunzhao Nie, Woogeun Rhee, Zhihua Wang
This paper describes a balanced frequency shift keying (FSK) modulation, namely quasi-balanced FSK (QB-FSK), for energy-efficient high-data-rate communication. Not suffering from data-pattern dependency, the proposed modulation method enables frequency modulation (FM) over 100 Mb/s by utilizing a wideband phase-locked loop (PLL). The QB-FSK signal is generated with the same baseband clock frequency