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Robust Clustering Using Hyperdimensional Computing IEEE Open J. Circuits Syst. Pub Date : 2024-03-26 Lulu Ge, Keshab K. Parhi
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A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing IEEE Open J. Circuits Syst. Pub Date : 2024-03-18 Manish Srivastava, Alessandro Ferro, Aleksandr Sidun, J.M. de la Rosa, Kilian O’Donoghue, Padraig Cantillon-Murphy, Daniel O’Hare
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Welcome to the 5th Volume of the Open Journal of Circuits and Systems IEEE Open J. Circuits Syst. Pub Date : 2024-02-07 Nicole McFarlane
Welcome to the 5th volume of the Open Journal of Circuits and Systems (OJCAS). The Circuits and Systems Society’s Gold Open Access Journal is maturing, welcoming more submissions and getting our first impact factor score. I welcome our new Associate Editor in Chief, Alex James of Digital University Kerala in Trivandrum India to help mature the journal even more. As the journal matures, it is important
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GC-Like LDPC Code Construction and Its NN-Aided Decoder Implementation IEEE Open J. Circuits Syst. Pub Date : 2024-02-06 Yu-Lun Hsu, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
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Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions IEEE Open J. Circuits Syst. Pub Date : 2024-01-30 Kamilya Smagulova, Mohammed E. Fouda, Ahmed Eltawil
The high speed, scalability, and parallelism offered by ReRAM crossbar arrays foster the development of ReRAM-based next-generation AI accelerators. At the same time, the sensitivity of ReRAM to temperature variations decreases $\text{R}_{ON}/\text{R}_{OFF}$ ratio and negatively affects the achieved accuracy and reliability of the hardware. Various works on temperature-aware optimization and remapping
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2023 Index IEEE Open Journal of Circuits and Systems Vol. 4 IEEE Open J. Circuits Syst. Pub Date : 2024-01-19
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An Efficient K-Best MIMO Detector for Large Modulation Constellations IEEE Open J. Circuits Syst. Pub Date : 2023-12-27 Yu-Xin Liu, Shih-Jie Jihang, Yeong-Luh Ueng
For K-best multiple-input multiple-output (MIMO) detection using real-valued decomposition (RVD), we need to obtain the $K$ surviving candidates from $K \sqrt {M}$ candidates, where $M$ is the modulation order. This paper presents a sorter-free detection algorithm, where the $K$ surviving nodes can be obtained in ${\mathrm {log_{2}}} {K}$ iterations, which is independent of modulation size. The $K
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IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering for Versatile Video Coding IEEE Open J. Circuits Syst. Pub Date : 2023-12-19 Yu-Han Sun, Chiang Lo-Hsuan Lee, Tian-Sheuan Chang
Image prefiltering with just noticeable distortion (JND) improves coding efficiency in a visual lossless way by filtering the perceptually redundant information prior to compression. However, real JND cannot be well modeled with inaccurate masking equations in traditional approaches or image-level subject tests in deep learning approaches. Thus, this paper proposes a fine-grained JND prefiltering dataset
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Asymptotic Performance Limitations in Cyberattack Detection IEEE Open J. Circuits Syst. Pub Date : 2023-12-04 Onur Toker
In this paper, we consider the difficulty of cyberattack detection with $d$ sensors and $n$ observations, and derive performance bounds that are valid independent of the attack detection algorithm used. In other words, regardless of whether it is an artificial intelligence (AI) or sensor fusion based approach or it is derived using a completely new innovative idea, a cyberattack detector using multiple
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Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers IEEE Open J. Circuits Syst. Pub Date : 2023-12-01 Yudhajit Ray, Shreyas Sen
Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like
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Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery IEEE Open J. Circuits Syst. Pub Date : 2023-11-27 Ahmed Abdelaziz, Mohamed Ahmed, Tawfiq Musah
This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector
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A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm IEEE Open J. Circuits Syst. Pub Date : 2023-11-15 Hamza Al Maharmeh, Nabil J. Sarhan, Mohammed Ismail, Mohammad Alhawari
The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes
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Class–CTA: Concept and Theoretical Analysis of a High Linearity and Efficiency Power Stage Architecture IEEE Open J. Circuits Syst. Pub Date : 2023-11-02 Dimitrios Baxevanakis, Dimitris Nikitas, Paul P. Sotiriadis
This work presents a power stage architecture that combines high–linearity with high–efficiency. The power stage is configured as a push–pull Class–A topology with two buck–converters providing its supply rails. The buck–converters continuously track the stage’s output with a small constant margin, creating a minimum, constant voltage drop on the output devices; thus, the stage’s efficiency is increased
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A Study of Out-of-Band Emission in Digital Transmitters Due to PLL Phase Noise, Circuit Non-Linearity, and Bandwidth Limitation IEEE Open J. Circuits Syst. Pub Date : 2023-11-02 Mohammad Oveisi, Seyedali Hosseinisangchi, Payam Heydari
A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized
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Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs IEEE Open J. Circuits Syst. Pub Date : 2023-08-29 Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures
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Reversible Gates: A Paradigm Shift in Computing IEEE Open J. Circuits Syst. Pub Date : 2023-08-15 Syed Farah Naz, Ambika Prasad Shah
The reversible gate has been one of the emerging research areas that ensure a continual process of innovation trends that explore and utilizes the resources. This review paper provides a comprehensive overview of reversible gates, including their fundamental principles, design methodologies, and various applications. It also analyzes the reversible gates, comparing them based on metrics such as Quantum
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Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure IEEE Open J. Circuits Syst. Pub Date : 2023-08-04 Archisman Ghosh, Debayan Das, Shreyas Sen
Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction
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Grant-Free Sparse Code Multiple Access for Uplink Massive Machine-Type Communications and Its Real-Time Receiver Design IEEE Open J. Circuits Syst. Pub Date : 2023-07-26 Ti-Yu Chen, Zhi-Jing Lin, Tzi-Dar Chiueh
Massive Machine-type Communications (mMTCs) is a major use case for the 5G standard. The grant-free (GF) sparse-coded multiple access (SCMA) transmission is particularly spectrum efficient in the sporadic uplink traffic, which is characteristic of the mMTC networks. In this paper, an uplink GF-SCMA receiver with a user activity detection (UAD) function was designed and implemented. In particular, several
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PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing IEEE Open J. Circuits Syst. Pub Date : 2023-07-24 Dong-Hyun Seo, Archisman Ghosh, Debayan Das, Mayukh Nath, Santosh Ghosh, Shreyas Sen
This paper presents the design and analysis of a pro-active strategy to detect the presence of an electromagnetic (EM) side-channel analysis (SCA) attack, using Patterned-Ground co-planar Capacitive Asymmetry Sensing (PG-CAS) system. The PG-CAS system senses the asymmetry created in the plate-ground capacitance and turns on a SCA countermeasure in presence of an EM probe. The proposed PG-CAS system
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Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization IEEE Open J. Circuits Syst. Pub Date : 2023-07-14 George Souliotis, Andreas Tsimpos, Spyridon Vlassis
In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, designed with the CMOS TSMC 65 nm process node. The CDR is based on an extended, in terms of phase resolution, version, with a novel PI topology proposed in
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Slimmer CNNs Through Feature Approximation and Kernel Size Reduction IEEE Open J. Circuits Syst. Pub Date : 2023-07-04 Dara Nagaraju, Nitin Chandrachoodan
Convolutional Neural Networks (CNNs) have been shown to achieve state of the art results on several image processing tasks such as classification, localization, and segmentation. Convolutional and fully connected layers form the building blocks of these networks. The convolution layers are responsible for the majority of the computations even though they have fewer parameters. As inference is used
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Deep Reinforcement Learning on FPGA for Self-Healing Cryogenic Power Amplifier Control IEEE Open J. Circuits Syst. Pub Date : 2023-06-05 Jiachen Xu, Yuyi Shen, Jinho Yi, Ethan Chen, Vanessa Chen
Wireless sensing and communication for space exploration in areas inaccessible to human often suffer from severe performance degradation due to the cryogenic effects on the transmitters’ circuits. To survive extreme temperatures, programmable radio frequency (RF) power amplifiers (PA) can be built into the transmitter, and intelligent PA controllers need to be integrated into the system to interact
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A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios IEEE Open J. Circuits Syst. Pub Date : 2023-04-26 Mathieu Xhonneux, Jérôme Louveaux, David Bol
We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are
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Polychronous Oscillatory Cellular Neural Networks for Solving Graph Coloring Problems IEEE Open J. Circuits Syst. Pub Date : 2023-03-27 Richelle L. Smith, Thomas H. Lee
This paper presents polychronous oscillatory cellular neural networks, designed for solving graph coloring problems. We propose to apply the Potts model to the four-coloring problem, using a network of locally connected oscillators under superharmonic injection locking. Based on our mapping of the Potts model to injection-locked oscillators, we utilize oscillators under divide-by-4 injection locking
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Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices IEEE Open J. Circuits Syst. Pub Date : 2023-03-20 Diptashree Das, Ziyue Xu, Mehdi Nasrollahpour, Isabel Martos-Repath, Mohsen Zaeimbashi, Adam Khalifa, Ankit Mittal, Sydney S. Cash, Nian X. Sun, Aatmesh Shrivastava, Marvin Onabajo
A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards
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An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS IEEE Open J. Circuits Syst. Pub Date : 2023-03-14 Liwen Lin, Ka-Meng Lei, Pui-In Mak, Rui P. Martins
This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager $(\mu $ PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such $\mu $ PM shows a high power efficiency by introducing
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A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting IEEE Open J. Circuits Syst. Pub Date : 2023-03-09 Troy Bryant, Yingjie Chen, David Selasi Koblah, Domenic Forte, Nima Maghari
As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal
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New Year Editorial 2023 IEEE Open J. Circuits Syst. Pub Date : 2023-03-01 Gabriele Manganaro, Nicole Mcfarlane
DEAR readers, happy 2023! I have recently been elected as the Vice President for Publications for the CAS Society for the 2023–2024 term. Because of that I am unable to complete my term as EiC, which would have otherwise elapsed on 31 December 2023. We are lucky to have two outstanding leaders, Alison Burdett and Nicole Mcfarlane, presently serving as Associate Editors-in-Chief (AEiC). The IEEE Circuits
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An On-Chip Fully Connected Neural Network Training Hardware Accelerator Based on Brain Float Point and Sparsity Awareness IEEE Open J. Circuits Syst. Pub Date : 2023-02-23 Tsung-Han Tsai, Ding-Bang Lin
In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other applications, gradually replacing traditional algorithms. It shows that the rise of neural networks has led to the reform of artificial intelligence. Since
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Adaptive Control Technique for Portable Solar Powered EV Charging Adapter to Operate in Remote Location IEEE Open J. Circuits Syst. Pub Date : 2023-02-22 Nishant Kumar, Harshit Kumar Singh, Roland Niwareeba
Every EV (Electric Vehicle) comes with limited energy storing capability. After travelling a certain distance, a charging facility is required to recharge the EV batteries, which is easy to be made available in cities. But, in remote locations, charging service is challenging. Therefore, big countries like USA, Canada, China, Russia, India, Australia, and few Arabian countries are planning to provide
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High Efficiency Power Management Unit for Implantable Optical-Electrical Stimulators IEEE Open J. Circuits Syst. Pub Date : 2023-01-30 Noora Almarri, Dai Jiang, Peter J. Langlois, Mohamad Rahal, Andreas Demosthenous
Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation
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Front Cover IEEE Open J. Circuits Syst. Pub Date : 2023-01-18
Presents the front cover for this issue of the publication.
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A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector IEEE Open J. Circuits Syst. Pub Date : 2023-01-18 Yanhan Zeng, Zhixian Li, Weijian Chen, Wei Zhou, Yuchen Bao, Yongsen Chen, Yongfu Li
This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal
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2022 Index IEEE Open Journal of Circuits and Systems Vol. 3 IEEE Open J. Circuits Syst. Pub Date : 2023-01-10
Presents the 2022 author/subject index for this issue of the publication.
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An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process IEEE Open J. Circuits Syst. Pub Date : 2023-01-12 Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami
In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring
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Table of Contents IEEE Open J. Circuits Syst. Pub Date : 2023-01-04
Presents the table of contents for this issue of the publication.
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Front Cover IEEE Open J. Circuits Syst. Pub Date : 2023-01-04
Presents the front cover for this issue of the publication.
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Comprehensive Mapping of Continuous/Switching Circuits in CCM and DCM to Machine Learning Domain Using Homogeneous Graph Neural Networks IEEE Open J. Circuits Syst. Pub Date : 2023-01-04 Ahmed K. Khamis, Mohammed Agamy
This paper proposes a method of transferring physical continuous and switching/converter circuits working in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) to graph representation, independent of the connection or the number of circuit components, so that machine learning (ML) algorithms and applications can be easily applied. Such methodology is generalized and is applicable
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Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers IEEE Open J. Circuits Syst. Pub Date : 2022-12-28 Hendrik P. Nel, Fortunato Carlos Dualibe, Tinus Stander
Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT
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Imitation System of Humanoid Robots and Its Applications IEEE Open J. Circuits Syst. Pub Date : 2022-12-21 Ze-Feng Zhan, Han-Pang Huang
In this paper, we propose an imitation system that imitates human motions in videos to plan robot actions that are similar to human motions, with the aim of the complicated whole-body action planning of humanoid robots. Additionally, we created an interaction system that will enable basic human-robot interaction for our humanoid robot. To obtain the 3D coordinates of the key points on the human body
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A Vision System With 1-inch 17-Mpixel 1000-fps Block-Controlled Coded-Exposure Stacked-CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control IEEE Open J. Circuits Syst. Pub Date : 2022-11-29 Tomoki Hirata, Hironobu Murata, Taku Arii, Hideaki Matsuda, Hajime Yonemochi, Yojiro Tezuka, Shiro Tsunai
This study introduces a vision system that can acquire images at high speeds and high resolutions. Image sensors are used not only in digital still cameras but also in various applications that require capturing wide luminance differences beyond human perception. For example, fast, high-resolution object recognition, and motion tracking in automatic driving systems are essential, particularly in dark
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A Nearly Interference-Free and Depth-Resolution-Configurable Time-of-Flight System Based on a Mega-Pixel Vertical Avalanche Photodiodes CMOS Image Sensor IEEE Open J. Circuits Syst. Pub Date : 2022-11-29 Shota Yamada, Motonori Ishii, Shigetaka Kasuga, Masato Takemoto, Hiromu Kitajima, Toru Okino, Yusuke Sakata, Manabu Usuda, Yugo Nose, Hiroshi Koshida, Masaki Tamaru, Akito Inoue, Yuki Sugiura, Shigeru Saito, Taiki Kunikyo, Yusuke Yuasa, Kentaro Nakanishi, Naoki Torazawa, Takashi Shirono, Tatsuya Kabe, Shinzo Koyama, Mitsuyoshi Mori, Yutaka Hirose, Masayuki Sawada, Akihiro Odagawa, Tsuyoshi Tanaka
We present a long range (~250 m) time-of flight (TOF) system with suppressed (nearly-free) mutual-interference. The system is based on a $1296\times960$ pixels vertical avalanche photodiodes (VAPD) CMOS image sensor (CIS). Real-time long-range 3D-imaging with 30 fps speed (450 fps for 2D imaging) is demonstrated. Designs and operation principles of the core circuits, i.e., a photon counting circuit
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Control Strategy of Three-Level NPC Inverter Based on Variable Coefficient Virtual Vector Model Predictive Control IEEE Open J. Circuits Syst. Pub Date : 2022-11-23 Weiquan Gu, Huangzheng Liao, Jiaqi Lin, Zewen Li, Tao Jin
The Conventional model predictive control (C-MPC) uses only a single voltage vector in each control period, resulting in poor control performance. In addition, the computational burden in discrete space state generated by three-level inverter cannot be ignored. To improve the control performance, this paper proposes a variable coefficient virtual vector MPC (VC-VV-MPC) method, a five-level virtual
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Editorial IEEE Open Journal of Circuits and Systems: Special Section on Advanced Power Electronics Techniques for Smart Grid Applications IEEE Open J. Circuits Syst. Pub Date : 2022-11-23 Mengqi Wang, Xiu Yao
The Advent of modern power electronics has brought tremendous impact on emerging power systems. In an emerging smart grid, as the number of inverter- and converter-based devices increases to more than hundreds of thousands, it is rather intuitive that the state-of-the-art technical solutions and industry practices will no longer be sustainable. The combination of power electronics and advanced control
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Droop-Controlled Bidirectional Inverter-Based Microgrid Using Cascade-Forward Neural Networks IEEE Open J. Circuits Syst. Pub Date : 2022-11-23 Mohamad Alzayed, Michel Lemaire, Sina Zarrabian, Hicham Chaoui, Daniel Massicotte
The voltage source inverters in microgrids often rely on the droop control method integrated with voltage and inner current control loops in order to provide a reliable electric power supply. This research aims to present a Cascade-Forward Neural Network (CFNN) droop control method that manages inverter-based microgrids under grid-connected/islanded operating modes. The proposed method operates the
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Introduction to the Special Section on Smart Imaging IEEE Open J. Circuits Syst. Pub Date : 2022-11-24 Ping-Hsuan Hsieh, Vanessa Chen
This Special Section of the IEEE Open Journal of Circuits and Systems is dedicated to a collection of articles on Smart Imaging, to promote techniques in both system and circuit levels to tackle various challenges as the requirements for image quality, efficiency, and levels of integration keep increasing and to provide insightful guidelines for intelligent vision in the years to come. This Special
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FPGA-Based Tensor Compressive Sensing Reconstruction Processor for Terahertz Single-Pixel Imaging Systems IEEE Open J. Circuits Syst. Pub Date : 2022-11-24 Wei-Chieh Wang, Yi-Chun Hung, Yu-Heng Du, Shang-Hua Yang, Yuan-Hao Huang
Terahertz (THz) imaging system has great potentials for material identification, security screening, circuit inspection, bioinformatics and bio-imaging because it can penetrate various non-metallic materials and inhibits unique spectral fingerprints of a great variety of optically opaque materials in our daily lives. However, THz emitters and detectors are still extremely expensive. Therefore, the
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IEEE Open Journal of Circuits and Systems Information for Authors IEEE Open J. Circuits Syst. Pub Date : 2022-10-28
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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Wang Algebra: From Theory to Practice IEEE Open J. Circuits Syst. Pub Date : 2022-10-26 Bob Ross, Cong Ling
Wang algebra was initiated by Ki-Tung Wang as a short-cut method for the analysis of electrical networks. It was later popularized by Duffin and has since found numerous applications in electrical engineering and graph theory. This is a semi-tutorial paper on Wang algebra, its history, and modern applications. We expand Duffin’s historic notes on Wang algebra to give a full account of Ki-Tung Wang’s
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A 2D Chaotic Oscillator for Analog IC IEEE Open J. Circuits Syst. Pub Date : 2022-10-25 Partha Sarathi Paul, Parker Hardy, Maisha Sadia, MD Sakib Hasan
In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic
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Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System IEEE Open J. Circuits Syst. Pub Date : 2022-10-04 Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone
This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller–Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer
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RF Analog Hardware Trojan Detection Through Electromagnetic Side-Channel IEEE Open J. Circuits Syst. Pub Date : 2022-09-28 John Kan, Yuyi Shen, Jiachen Xu, Ethan Chen, Jimmy Zhu, Vanessa Chen
With the advent of globalization, hardware trojans provide an ever-present threat to the security of devices. Much of the research to date has centered around documenting and providing detection methods for digital trojans. Few, however, have explored the space of trojans in the RF/analog front end. Two hardware trojans, an analytical analysis of the trojan impacts on two different types of amplifiers
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UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications IEEE Open J. Circuits Syst. Pub Date : 2022-09-26 Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
An error floor phenomenon, decoding performance, and throughput are three major concerns for LDPC decoders in NAND Flash applications. With a penalty method and an active iteration mechanism, we present a Unified Penalty Gradient Descent Bit Flipping (UP-GDBF) decoding algorithm, which not only possesses error-floor free property but also improves convergence speed in decoding performance. To fulfill
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IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022 IEEE Open J. Circuits Syst. Pub Date : 2022-09-20 Alison Burdett
The International Symposium on Integrated Circuits and Systems (ISICAS) is a forum for dissemination of original work with experimental results from integrated circuits and systems in the areas of analog, digital, power, energy, biomedical, sensor interfaces and communications. Papers accepted to be presented at the symposium are automatically published in special issues of leading IEEE Circuits and
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SEKV-E: Parameter Extractor of Simplified EKV I-V Model for Low-Power Analog Circuits IEEE Open J. Circuits Syst. Pub Date : 2022-09-20 Hung-Chi Han, Antonio D’Amico, Christian Enz
This paper presents the open-source Python-based parameter extractor (SEKV-E) for the simplified EKV (sEKV) model, which enables the modern low-power circuit designs with the inversion coefficient design methodology. The tool extracts the essential sEKV parameters automatically from the given $I$ - $V$ curves using the direct extraction and the multi-stage optimization process. It also handles the
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Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional Neural Networks IEEE Open J. Circuits Syst. Pub Date : 2022-09-20 Jinho Yi, Jiachen Xu, Ethan Chen, Maysamreza Chamanzar, Vanessa Chen
Real-time in-sensor spike sorting is a forefront requirement in the development of brainmachine interfaces (BMIs). This work presents the characterization, design, and efficient implementation on a field-programmable gate array (FPGA) of a novel approach to neural spike sorting intended for implantable devices based on convolutional neural networks (CNNs). While the temporal features, the shape of
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Demonstrating Analog Inference on the BrainScaleS-2 Mobile System IEEE Open J. Circuits Syst. Pub Date : 2022-09-21 Yannik Stradmann, Sebastian Billaudelle, Oliver Breitwieser, Falk Leonard Ebert, Arne Emmel, Dan Husmann, Joscha Ilmberger, Eric Müller, Philipp Spilger, Johannes Weis, Johannes Schemmel
We present the BrainScaleS-2 mobile system as a compact analog inference engine based on the BrainScaleS-2 ASIC and demonstrate its capabilities at classifying a medical electrocardiogram dataset. The analog network core of the ASIC is utilized to perform the multiply-accumulate operations of a convolutional deep neural network. At a system power consumption of 5.6W, we measure a total energy consumption