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Fuzzing for Automated SoC Security Verification: Challenges and Solution IEEE Des. Test (IF 2.0) Pub Date : 2024-03-18 Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
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Conventional Tests for Approximate Scan Logic IEEE Des. Test (IF 2.0) Pub Date : 2024-02-26 Irith Pomeranz
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Report on the 2023 Embedded Systems Week (ESWEEK) IEEE Des. Test (IF 2.0) Pub Date : 2024-02-21 Xiaobo Sharon Hu, Alain Girault, Heiko Falk
Embedded Systems Week (ESWEEK) is the premier worldwide event covering all aspects of embedded systems, encompassing software, hardware, and codesign aspects. Since its creation in 2005, it has gathered three leading conferences (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES; International Conference on Hardware/Software Codesign and System Synthesis
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Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security IEEE Des. Test (IF 2.0) Pub Date : 2024-02-21 Partha Pratim Pande
The articles in this issue are divided into three groups: 1) the first group are articles in the Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security; 2) the second group comprises general interest articles; and 3) additionally, we have two conference reports.
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Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security IEEE Des. Test (IF 2.0) Pub Date : 2024-02-21 Gang Qu
The globalization of IC design is forcing IC and IP core designers and users to reconsider the security and trust of hardware as the semiconductor industry is losing multiple billions of dollars annually due to IP infringement. An attacker can reverse engineer the functionality of an IC/IP, steal and claim ownership of the IP, inject malicious circuitry into the IC, introduce counterfeits into the
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Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023) IEEE Des. Test (IF 2.0) Pub Date : 2024-02-21 Evangeline Young
This Year Marks our return to a fully in-person International Conference on Computer-Aided Design (ICCAD) after the COVID-19 pandemic. We are thrilled to resume an event with personal interactions and extensive networking while retaining some good practices adopted during the pandemic of having a virtual platform where participants and authors can connect remotely.
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Predictions IEEE Des. Test (IF 2.0) Pub Date : 2024-02-21 Scott Davidson
We engineers do a lot of predicting. When we design something, we predict how it will perform when implemented. We use tools like simulators and timing analyzers to help us refine these predictions, but getting silicon that runs as fast as you had hoped it would run is always a pleasant surprise.
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A BIST Approach to Approximate Co-Testing of Embedded Data Converters IEEE Des. Test (IF 2.0) Pub Date : 2024-02-14 Kushagra Bhatheja, Shravan Chaganti, Johnathan Leisinger, Emmanuel Nti Darko, Issac Bruce, Degang Chen
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Testing for Multiple Faults in Deep Neural Networks IEEE Des. Test (IF 2.0) Pub Date : 2024-02-13 Dina A. Moussa, Michael Hefenbrock, Mehdi Tahoori
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Efficient Aspect Verification and Debug of High-Performance Microprocessor Designs IEEE Des. Test (IF 2.0) Pub Date : 2024-02-06 Arun Joseph, Pretty Mariam Jacob, Matthias Klein, Wolfgang Roesner
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Ethics in Computing IEEE Des. Test (IF 2.0) Pub Date : 2024-01-17 Partha Pratim Pande
The articles in this issue are divided into three groups: 1) the first group comprises the Special Issue on Ethics in Computing articles; 2) the second group consists of general interest articles; and 3) additionally, we have a tutorial article in this issue.
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Special Issue on Ethics in Computing IEEE Des. Test (IF 2.0) Pub Date : 2024-01-17 Sudeep Pasricha, Marilyn Wolf
Computing systems are tightly integrated today into our professional, social, and private lives. These systems span the gamut of wearables and smart home Internet of Things (IoT) edge devices, to automotive cyber-physical systems (CPS), and massive cloud computing data center facilities. An important consequence of this growing ubiquity of computing is that it can have significant ethical implications
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The 28th IEEE European Test Symposium IEEE Des. Test (IF 2.0) Pub Date : 2024-01-17 Naghmeh Karimi
The 28th IEEE European Test Symposium (ETS) was held in Venice, Italy, 22–26 May 2023, in a hybrid format. This was the second hybrid venue for ETS since the COVID-19 pandemic. ETS is Europe’s premier forum in the area of electronic-based circuits and system testing, reliability, security, and validation. ETS’23 was arranged in five days and the program consisted of keynotes, scientific paper presentations
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ISLPED 2023: International Symposium on Low-Power Electronics and Design IEEE Des. Test (IF 2.0) Pub Date : 2024-01-17 Axel Jantsch, Swaroop Ghosh, Umit Ogras, Pascal Meinerzhagen
The ISLPED 2023 conference was held as a presence-only event from 6 to 8 August 2023, at the premises of the Technische Universität TU Wien near the center of Vienna, Austria. It was the first presence-only meeting after the disruption due to the COVID-19 pandemic, which was very much enjoyed by all delegates. 35 full papers and 18 posters were presented in two parallel sessions. Also, two keynote
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Losing My Memory IEEE Des. Test (IF 2.0) Pub Date : 2024-01-17 Scott Davidson
I was happy to see the article on estimating memory usage by Yoon et al. in this issue of IEEE Design&Test . I have not seen much work on this subject lately. I have heard those who do software for embedded systems rightly express pride in how efficiently they write code but judging from the memory usage data on programs I run on my laptop, many modern software developers are allergic to the system
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Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking IEEE Des. Test (IF 2.0) Pub Date : 2024-01-15 Prabuddha Chakraborty, Jonathan Cruz, Rasheed Almawzan, Tanzim Mahfuz, Swarup Bhunia
This article argues the need for structural security in securing logic locking against learning-based attacks.
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Spectre Returns! Speculation Attacks Using the Return Stack Buffer IEEE Des. Test (IF 2.0) Pub Date : 2024-01-10 Esmaeil Mohammadian Koruyeh, Khaled N. Khasawneh, Chengyu Song, Nael Abu-Ghazaleh
This article describes a new Spectre-class attack that exploits the return stack buffer and does not rely on the branch predictor unit.
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The 2023 Networks-on-Chip (NOCS) Symposium IEEE Des. Test (IF 2.0) Pub Date : 2023-10-20 Partha Pratim Pande
The highlight of this issue is the journal-first model adopted for the articles accepted in the 17th edition of the Networks-on-Chip (NOCS) Symposium. NOCS is held in conjunction with the Embedded Systems Week (ESWEEK). This year, NOCS was held in Hamburg, Germany, on 21–22 September 2023, marking its return to a fully in-person symposium after virtual and hybrid editions during the pandemic. NOCS
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Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023) IEEE Des. Test (IF 2.0) Pub Date : 2023-10-20 Mahdi Nikdast, Miquel Moreto, Masoumeh Azin Ebrahimi, Sujay Deb
The International Symposium on networks-on-chip (NOCS) serves as the premier interdisciplinary meeting for research on NoC architecture, implementation, analysis, optimization, and verification, encompassing various aspects of NoCs for embedded high-performance computing systems, un-core and system-level NoCs, inter/intrachip, and rack-scale networks. Similar to previous years, this event has been
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VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network IEEE Des. Test (IF 2.0) Pub Date : 2023-09-18 Yuxuan Pan, Zhonghua Zhou, S. Arash Sheikholeslam, André Ivanov
Detailed routing is a challenging step of the physical design process, causing design rule violations and significant time costs. This article presents VioNet, a machine-learning framework that predicts the most common violations from a placed netlist. By using global routing congestion estimation instead of actual routing results, VioNet achieves substantial speedup.
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Hardware/Software Coexploration for Hyperdimensional Computing on Network-on-Chip Architecture IEEE Des. Test (IF 2.0) Pub Date : 2023-09-04 Junhuan Yang, Lei Yang
This article introduces a hardware/software coexploration framework based on neural architecture search, aimed at optimizing the deployment of hyperdimensional computing (HDC) on Network-on-Chip (NoC) architecture.
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SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs IEEE Des. Test (IF 2.0) Pub Date : 2023-08-30 Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P. Carloni
Editor’s notes: This article introduces a novel debug unit enabling compositional postsilicon validation of heterogeneous SoCs. The unit’s effectiveness is demonstrated in post-silicon validation by integrating it into a 12-nm complex SoC prototype. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute of
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A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow IEEE Des. Test (IF 2.0) Pub Date : 2023-08-30 Lingxiao Zhu, Wenjie Fan, Chenyang Dai, Shize Zhou, Yongqi Xue, Zhonghai Lu, Li Li, Yuxiang Fu
This article addresses the challenges of excessive storage overhead and the absence of sparsity-aware design in Network-on-Chip (NoC)-based spatial deep neural network accelerators. The authors present a prototype chip that outperforms existing accelerators in both energy and area efficiency, demonstrated on TSMC 28-nm process technology. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto
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SPOCK: Reverse Packet Traversal for Deadlock Recovery IEEE Des. Test (IF 2.0) Pub Date : 2023-08-30 Zeyu Chen, Ankur Bindal, Vaidehi Garg, Tushar Krishna
In this article, the authors leverage a probe-based deadlock detection system and propose a deadlock recovery mechanism for interconnection networks.
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Similarity-Based Fast Analysis of Data Center Networks IEEE Des. Test (IF 2.0) Pub Date : 2023-08-30 Shruti Yadav Narayana, Emily Shriver, Kenneth O’Neal, Nuriye Yildirim, Khamida Begaliyeva, Umit Y. Ogras
The authors in this article present a novel similarity-based technique that clusters similar flows, achieving high speedups without compromising accuracy.
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Fast Analysis Using Finite Queuing Model for Multilayer NoCs IEEE Des. Test (IF 2.0) Pub Date : 2023-08-30 Shruti Y. Narayana, Sumit K. Mandal, Raid Ayoub, Mohammad M. Islam, Michael Kishinevsky, Umit Y. Ogras
This article introduces a performance analysis technique that accounts for interlayer dependencies in multilayer Networks-on-Chip (NoCs). This technique is based on estimating queuing delays and blocking probabilities between layers.
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The 2022 Symposium on Integrated Circuits and Systems Design (SBCCI 2022) IEEE Des. Test (IF 2.0) Pub Date : 2023-08-28 Partha Pratim Pande
The articles in this issue are divided into two groups: 1) the first group comprises articles from the 2022 Symposium on Integrated Circuits and Systems Design (SBCCI 2022), and 2) the second group consists of general interest articles.
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SBCCI 2022 IEEE Des. Test (IF 2.0) Pub Date : 2023-08-28 Nuno Roma, Bruno Zatt
The Symposium on ICs and Systems Design (SBCCI) is an international forum dedicated to ICs and systems design, test, and EDA, held annually in Brazil. Over the past four decades, SBCCI has established itself as an important international forum for the presentation of research results on leading-edge aspects of ICs and systems, such as analog circuits, mixed-signal and digital ICs design, dedicated
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Postpandemic Conferences: The DATE 2023 Experience IEEE Des. Test (IF 2.0) Pub Date : 2023-08-28 Ian O’Connor, Robert Wille, Andy D. Pimentel, Valeria Bertacco
Date is a leading international event providing unique networking opportunities. The conference brings together designers and design automation users, researchers, and vendors, as well as specialists in hardware and software design, testing, and manufacturing of electronic circuits and systems—from system-level hardware and software implementation down to integrated circuit design.
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The 41st IEEE VLSI Test Symposium IEEE Des. Test (IF 2.0) Pub Date : 2023-08-28 Naghmeh Karimi
The 41st IEEE VLSI Test Symposium (VTS) was held in San Diego, CA, USA, on 24–26 April 2023. This venue was the first in-person one since the COVID-19 pandemic. VTS is one of the premier conferences focusing on test, reliability, and security challenges in VLSI circuits. Following the same trend as prior years, VTS was arranged in three days and captured a set of research and innovative practice (IP)
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Calling Yourself Back IEEE Des. Test (IF 2.0) Pub Date : 2023-08-28 Scott Davidson
I recently saw a performance where the premise was that the performer could talk to his former self at various times in his life. For instance, he told himself at 20 that he would survive breaking up with his first true love. The other calls were similar critical points of his past. He briefly mentioned the kind of time travel paradoxes this could cause, for instance, the self who bought Apple stock
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Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System IEEE Des. Test (IF 2.0) Pub Date : 2023-08-29 Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
This article presents an approach to address challenges in shapechangeable computer systems, offering methods for ad hoc wireless network construction, routing, and dynamic reconfiguration based on nearfield inductive coupling between on-chip coils.
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ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training IEEE Des. Test (IF 2.0) Pub Date : 2023-08-29 K. Neethu, K. C. Sharin Shahana, Rekha K. James, John Jose, Sumit K. Mandal
In this article, an architecture for in-memory computing (IMC)-based 2.5-D systems with multiple Network-on-Package (NoP) components is proposed.
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Automated Optical Accelerator Search: Expediting Green and Ubiquitous DNN-Powered Intelligence IEEE Des. Test (IF 2.0) Pub Date : 2023-08-29 Mingfeng Lan, Mengquan Li, Jie Xiong, Weichen Liu, Chubo Liu, Kenli Li
Editor’s notes: In this article, the authors develop a systematized framework to achieve automated optical accelerator architecture search. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden —Sujay Deb, IIIT Delhi, India
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Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs IEEE Des. Test (IF 2.0) Pub Date : 2023-08-29 Ibrahim Krayem, Joel Ortiz Sosa, Cédric Killian, Daniel Chillet
This article presents an analytical model based on queuing theory to evaluate the latency of many-core architecture interconnects, particularly focusing on hybrid interconnections combining electrical and wireless Networks-on-Chip (NoCs).
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A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip IEEE Des. Test (IF 2.0) Pub Date : 2023-08-25 Kamil Khan, Sudeep Pasricha
In this article, the authors introduce a regional congestion-aware reinforcement learning (RL)-based routing policy for Network-on-Chip (NoC) architectures.
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PiN: Processing in Network-on-Chip IEEE Des. Test (IF 2.0) Pub Date : 2023-08-24 Zhonghai Lu
The author in this article advocates for Processing in NoC (PiN) as a means to actively engage a Network-on-Chip (NoC) in computation. The article highlights the benefits of utilizing the communication network for system-level performance enhancement, with a case study demonstrating its advantages over conventional passive NoC approaches. y Deb, IIIT Delhi, India
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Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature IEEE Des. Test (IF 2.0) Pub Date : 2023-08-22 Mahendra Rathor, Girraj Prasad Rathor
IP protection is extremely important due to distributed hardware development. Signature-based IP protection provides a useful approach for the same. In this article, the authors propose a technique using handwritten signatures to be used as watermarks for protecting hardware.
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On Hardware-Aware Design and Optimization of Edge Intelligence IEEE Des. Test (IF 2.0) Pub Date : 2023-08-22 Shuo Huai, Hao Kong, Xiangzhong Luo, Di Liu, Ravi Subramaniam, Christian Makaya, Qian Lin, Weichen Liu
In this article, the authors explore recent efforts in hardware-aware design and optimization for edge intelligence. The article focuses on techniques such as model compression and neural architecture search to enhance system efficiency and effectiveness.
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FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic IEEE Des. Test (IF 2.0) Pub Date : 2023-08-21 Tim Fischer, Michael Rogenmoser, Matheus Cavalcante, Frank K. Gürkaynak, Luca Benini
This article introduces an open-source, low-latency Network-on-Chip (NoC) designed to tackle bandwidth challenges faced by traditional narrow and serialized NoCs. The authors demonstrate the effectiveness of wide channels by integrating a 5 × 5 router and links within a 9-core compute cluster using 12-nm FinFet technology.
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edAttack: Hardware Trojan Attack on On-Chip Packet Compression IEEE Des. Test (IF 2.0) Pub Date : 2023-08-21 Atul Kumar, Dipika Deb, Shirshendu Das, Palash Das
In this article, the authors investigate the prospect of a new hardware trojan (HT) in Network-on-Chip (NoC) routers or network interfaces (NIs), targeting on-chip packet compression techniques.
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Intellectual Property Protection of Deep-Learning Systems via Hardware/Software Co-Design IEEE Des. Test (IF 2.0) Pub Date : 2023-08-09 Huili Chen, Cheng Fu, Bita Darvish Rouhani, Jishen Zhao, Farinaz Koushanfar
Editor’s notes: This article protects deep learning models by leveraging hardware device-specific model fingerprinting and trusted execution environment. —Gang Qu, University of Maryland, USA
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Furthering Moore’s Law Integration Benefits in the Chiplet Era IEEE Des. Test (IF 2.0) Pub Date : 2023-08-07 Rob Munoz
Aggressive technology scaling, which has fueled the remarkable growth of the semiconductor industry for past decades, is faced with several fundamental barriers. Under this setting, chiplet technology, which promotes a modular, multidie integration approach to build complex chips in 2.5-D/3-D packages, has shown great promise to further the Moore’s law. This tutorial article focuses on the motivation
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Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology IEEE Des. Test (IF 2.0) Pub Date : 2023-07-12 Zhan Gao, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen
This article describes a method to improve test quality by explicitly targeting realistic cell-internal open and short defects through dedicated technology cell-level test patterns. The authors report some of the earliest results of their cell-aware test methods on an advanced 3-nm technology library from IMEC.
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FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs) IEEE Des. Test (IF 2.0) Pub Date : 2023-06-30 Anish Krishnakumar, Hanguang Yu, Tutu Ajayi, A. Alper Goksoy, Vishrut Pandey, Joshua Mack, Sahil Hassan, Kuan-Yu Chen, Chaitali Chakrabarti, Daniel W. Bliss, Ali Akoglu, Hun-Seok Kim, Ronald G. Dreslinski, David Blaauw, Umit Y. Ogras
This article presents FALCON, a full-system domain-specific system-onchip emulation platform that enables presilicon power and performance estimation of these platforms to provide support for early functional validation and software development.
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Designing Secure TLBs IEEE Des. Test (IF 2.0) Pub Date : 2023-06-27 Shuwen Deng, Wenjie Xiong, Jakub Szefer
This article reveals timing-based side-channel and covert-channel attacks from the translation look-aside buffers (TLBs) and discusses how to design secure TLBs.
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Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis IEEE Des. Test (IF 2.0) Pub Date : 2023-06-26 Stjepan Picek, Annelie Heuser, Alan Jovic, Shivam Bhasin, Francesco Regazzoni
This article reports the latest progress on the imbalance problem in evaluating the performance of machine-learning-based side-channel analysis.
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40th IEEE VLSI Test Symposium 2022 IEEE Des. Test (IF 2.0) Pub Date : 2023-06-15 Partha Pratim Pande
The articles in this issue are divided into two groups: 1) the first group comprises selected articles from the 40th IEEE VLSI Test Symposium 2022 and 2) the second group consists of general interest articles.
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Our Gated Community IEEE Des. Test (IF 2.0) Pub Date : 2023-06-15 Scott Davidson
Many cities in Europe still have walls left over from an earlier era. I have been to the walls in Tallinn, Estonia, and Valetta, Malta, which is particularly impressive as you approach the harbor from the sea. These walls were built to keep out invading armies, but they also kept out bandits and small bands of marauders. Inside the walls, the residents were relatively safe.
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Memory Usage Estimation for Dataflow-Model-Based Software Development Methodology IEEE Des. Test (IF 2.0) Pub Date : 2023-06-14 Kyonghwan Yoon, EunJin Jeong, Woosuk Kang, Soonhoi Ha
Software designed to run on memory-limited embedded platforms must not violate peak memory requirements. This article proposes a memory usage estimation technique in a model-based software development methodology to meet these goals for code that is synthesized from a dataflow-model-based specification. —Sudeep Pasricha, Colorado State University, USA
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Integrating Machine-Learning Probes in FPGA CAD: Why and How? IEEE Des. Test (IF 2.0) Pub Date : 2023-06-14 Timothy Martin, Charlotte Barnes, Gary Grewal, Shawki Areibi
Editor’s notes: This article discusses challenges posed by current designs and proposes the adoption of machine-learning probes in the FPGA design flow to improve performance. —Nuno Roma, Instituto Superior Técnico (IST), Universidade de Lisboa, Portugal —Bruno Zatt, Federal University of Pelotas (UFPel), Pelotas, Brazil
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Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction IEEE Des. Test (IF 2.0) Pub Date : 2023-06-14 Marcel Corrêa, Daniel Palomino, Guilherme Corrêa, Luciano Agostini
Editor’s notes::This article presents a fast mode decision scheme and a mode-adaptive subsampling algorithm to accelerate AV1 encoding.—Nuno Roma, Instituto Superior Técnico (IST), Universidade de Lisboa, Portugal —Bruno Zatt, Federal University of Pelotas (UFPel), Pelotas, Brazil
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Seamless Thermal Optimization of Parallel Workloads IEEE Des. Test (IF 2.0) Pub Date : 2023-06-14 Sandro Matheus Vila Nova Marques, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon
Editor’s notes: This article proposes a framework for thread-throttling and core-frequency optimization. The framework titled TAURUS is dynamic and transparent to the end user. —Nuno Roma, Instituto Superior Técnico (IST), Universidade de Lisboa, Portugal —Bruno Zatt, Federal University of Pelotas (UFPel), Pelotas, Brazil