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A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design

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Abstract

In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments of three important aspects related to hardware/software partitioning, which has great effects on the performance of embedded systems. Firstly, various partitioning models including hardware architectures and abstract models are surveyed. Secondly, classical and new algorithms for hardware/software partitioning are classified and analyzed. Thirdly, existing parallel algorithms for hardware/software co-design are discussed in details. Finally, possible research directions are pointed out in conclusion.

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References

  1. De Michell G, Gupta RK (1997) Hardware/software co-design. Proc IEEE 5(3):349–365

    Google Scholar 

  2. Wolf W (2003) A decade of hardware/software co-design. Computer 6(4):8–43

    Google Scholar 

  3. Teich J (2012) Hardware/software co-design: the past, the present, and predicting the future. Proc IEEE 100:1411–1430

    Google Scholar 

  4. Prakash S, Parker AC (1992) Synthesis of application-specific heterogeneous multiprocessor systems. In: Proceedings of the 19th annual international symposium on computer architecture, IEEE, p 434

  5. Gupta RK, De Micheli G (1993) Hardware–software co-synthesis for digital systems. IEEE Des Test Comput 10(3):29–41

    Google Scholar 

  6. Ernst R, Henkel J, Benner T (1993) Hardware–software co-synthesis for micro-controllers. IEEE Des Test Comput 10(4):64–75

    Google Scholar 

  7. Buck J, Ha S, Lee EA, Messerschmitt DG (1994) Ptolemy: a framework for simulating and prototyping heterogeneous systems. Int J Comput Sim 4:155–182

    Google Scholar 

  8. Li YTS, Malik S, Wolfe A (1999) Performance estimation of embedded software with instruction cache modeling. ACM Trans Des Autom Electron Syst 4(3):257–279

    Google Scholar 

  9. Thiele L, Chakraborty S, Naedele M (2000) Real-time calculus for scheduling hard real-time systems. In: Proceedings of the 2000 IEEE international symposium on Geneva, IEEE, pp. 101–104

  10. Blickle T, Teich J, Thiele L (1998) System-level synthesis using evolutionary algorithms. Des Autom Embed Syst 3(1):23–58

    Google Scholar 

  11. Ernst R (1998) Codesign of embedded systems: status and trends. IEEE Des Test Comput 15(2):45–54

    Google Scholar 

  12. Keinertn J, Streubuhr M, Schlichter T, Falk J, Gladigau J, Haubelt C, Teich J, Meredith M (2009) SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans Des Autom Electron Syst 14(1):1–23

    Google Scholar 

  13. Gerstlauer A, Haubelt C, Pimentel AD, Stefanov TP, Gajski DD, Teich J (2009) Electronic system-level synthesis methodologies. IEEE Trans Comput Aid Des Int 28(10):1517–1530

    Google Scholar 

  14. Park HW, Oh H, Ha S (2009) Multiprocessor SoC design methods and tools. IEEE Signal Process Mag 26(6):72–79

    Google Scholar 

  15. Hannig F, Teich J (2001) Design space exploration for massively parallel processor arrays. In: International conference on parallel computing technologies. Springer, Berlin, pp 51–65

  16. Erbas C, Cerav-Erbas S, Pimentel AD (2006) Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Trans Evol Comput 10(3):358–374

    Google Scholar 

  17. Deb K, Pratap A, Agarwal S, Meyarivan T (2002) A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans Evol Comput 6(2):182–197

    Google Scholar 

  18. Lukasiewycz M, Glab M, Haubelt C, Teich J (2008) Efficient symbolic multi-objective design space exploration. In: Proceedings of the 2008 Asia and South Pacific design automation conference. IEEE Computer Society Press, pp 691–696

  19. Zebelein C, Falk J, Haubelt C, Teich J (2008) Classification of general data flow actors into known models of computation. In: Proceedings of sixth ACM and IEEE international conference on formal methods and models for co-design, IEEE, pp. 119–128

  20. Wolff FG, Knieser MJ, Weyer DJ, Papachristou CA (1999) Using codesign techniques to support analog functionality. In: Proceedings of the seventh international workshop on Hardware/software codesign, ACM, pp. 79–84

  21. Dubach C, Jones TM, O’Boyle MFP (2008) Exploring and predicting the architecture optimising compiler co-design space. In: Proceedings of the 2008 international conference on compilers, architectures and synthesis for embedded systems, ACM, pp. 31–40

  22. Samii S, Cervin A, Eles P, Peng Z (2009) Integrated scheduling and synthesis of control applications on distributed embedded systems. In: Proceedings of the conference on design, automation and test in Europe. European Design and Automation Association, pp. 57–62

  23. Engel M, Schmoll F, Heinig A, Marwedel P (2011) Unreliable yet useful-reliability annotations for data in cyber-physical systems. In: Proceedings of the workshop on software language engineering for cyber-physical systems, Berlin, Germany

  24. Haubelt C, Koch D, Reimann F, Streichert T, Teich J (2010) ReCoNetsVDesign methodology for embedded systems consisting of small networks of reconfigurable nodes and connections. Dynamically reconfigurable systems. Springer, Dordrecht, pp 223–243

    Google Scholar 

  25. Zhang Y, Luo W, Zhang Z, Li B, Wang X (2008) A hardware/software partitioning algorithm based on artificial immune principles. Appl Soft Comput 8(1):383–391

    Google Scholar 

  26. Wu JG, Sun QQ, Srikanthan T (2012) Algorithmic aspects for multiple-choice hardware/software partitioning. Comput Oper Res 39(12):3281–3292

    MATH  Google Scholar 

  27. Sha E, Wang L, Zhuge Q, Zhang J, Liu J (2015) Power efficiency for hardware/software partitioning with time and area constraints on MPSoC. Int J Parallel Program 43(3):381–402

    Google Scholar 

  28. Ouyang A, Peng X, Liu J, Sallam A (2017) Hardware/software partitioning for heterogeneous MPSoC considering communication overhead. Int J Parallel Program 45(4):1–24

    Google Scholar 

  29. Jemai M, Ouni B (2015) Hardware software partitioning of control data flow graph on system on programmable chip. Microprocess Microsyst 39(4–5):259–270

    Google Scholar 

  30. Santos R, Venkataraman S, Kumar A (2017) Scrubbing mechanism for heterogeneous applications in reconfigurable devices. ACM Trans Des Autom Electron Syst 22(2):33

    Google Scholar 

  31. Das AK, Kumar A, Veeravalli B, Catthoor F (2018) Reliability and energy-aware co-design of multiprocessor systems. Reliable and energy efficient streaming multiprocessor systems. Springer, Cham, pp 75–101

    Google Scholar 

  32. Cardoso J, Hubner M (eds) (2011) Reconfigurable computing: from FPGAs to hardware/software co-design. Springer, Berlin

    Google Scholar 

  33. Ha S, Teich J (eds) (2017) Handbook of hardware/software co-design. Springer, Dordrecht

    Google Scholar 

  34. Zhao X, Zhang T, An X, Fan L (2018) An improved blind optimization algorithm for hardware/software partitioning and scheduling. In: International conference on sensing and imaging. Springer, Cham, pp 225–234

  35. Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M (2018) R-Codesign: codesign methodology for real-time reconfigurable embedded systems under energy constraints. IEEE Access 6:14078–14092

    Google Scholar 

  36. Ali AAS, Farhat A, Mohamad S, Amira A, Bensaali F, Benammar M, Bermak A (2018) Embedded platform for gas applications using hardware/software co-design and RFID. IEEE Sens J 18(11):4633–4642

    Google Scholar 

  37. Resano J, Mozos D, Catthoor F (2005) A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware. In: Proceedings of the conference on design, automation and test in Europe. IEEE Computer Society, pp 106–111

  38. Jerraya AA, Wolf W (2005) Hardware/software interface co-design for embedded system. Computer 38(2):63–69

    Google Scholar 

  39. Patterson DA, Hennessy JL (2013) Computer organization and design MIPS edition: the hardware/software interface. Morgan Kaufmann, Waltham

    Google Scholar 

  40. Villarraga C, Schmidt B, Bao B, Raman R, Bartsch C, Fehmel T, Stoffel D, Kunz W (2014) Software in a hardware view: new models for HW-dependent software in SoC verification and test. In: 2014 IEEE international test conference (ITC), IEEE, pp 1–9

  41. Purandare M (2018) Method for verifying hardware/software co-designs. U.S. Patent, No. 9,996,637

  42. Jerraya AA, Bouchhima A, Petrot F (2006) Programming models and HW–SW interfaces abstraction for multi-processor SoC. In: Proceedings of the 43rd annual design automation conference, ACM, pp 280–285

  43. Hut S (2015) A clustering-based MPSoC design flow for data flow-oriented applications. Ph.D. Dissertation, Friedrich-Alexander-Universitat Erlangen-Nurnberg

  44. Rigge P, Nikolic B (2018) Designing digital signal processors with RocketChip. In: Second workshop on computer architecture research with RISC-V (CARRV 2018)

  45. Dick RP, Jha NK (1998) MOGAC: a multi-objective genetic algorithm for hardware–software co-synthesis of distributed embedded systems. IEEE Trans Comput Aid Des Int 17(10):920–935

    Google Scholar 

  46. Erbas C, Cerav-Erbas S, Pimentel AD (2006) Multi-objective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Trans Evol Comput 10(3):358–374

    Google Scholar 

  47. Govil N, Shrestha R, Chowdhury SR (2017) PGMA: an algorithmic approach for multi-objective hardware software partitioning. Microprocess Microsyst 54:83–96

    Google Scholar 

  48. Nath PK, Datta D (2014) Multi-objective hardware–software partitioning of embedded systems: a case study of JPEG encoder. Appl Soft Comput 15(2):30–41

    Google Scholar 

  49. Shi W, Wu J, Lam S, Srikanthan T (2016) Algorithms for bi-objective multiple-choice hardware/software partitioning. Comput Electr Eng 50:127–142

    Google Scholar 

  50. Henkel J, Ernst R (2001) An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques. IEEE Trans Very Large Scale Integr 9(2):273–289

    Google Scholar 

  51. Schaumont PR (2012) A practical introduction to hardware/software co-design. Springer, Berlin

    Google Scholar 

  52. Dick R, Rhodes D, Wolf W (1998) TGFF: task graphs for free. In: Proceedings of the 6th international workshop on Hardware/software codesign. IEEE Computer Society, pp 97–101

  53. Jiang G, Wu J, Lam SK, Srikanthan T, Sun J (2015) Algorithmic aspects of graph reduction for hardware/software partitioning. J Supercomput 71(6):2251–2274

    Google Scholar 

  54. Madsen J, Grode J, Knudsen PV, Petersen ME, Haxthausen A (1997) LYCOS: the Lyngby co-synthesis system. Des Autom Embed Syst 2(2):195–235

    Google Scholar 

  55. Jigang W, Srikanthan T (2006) Low-complex dynamic programming algorithm for hardware/software partitioning. Inf Process Lett 98(2):41–46

    MATH  Google Scholar 

  56. Wu J, Srikanthan T, Yan C (2008) Algorithmic aspects for area-efficient hardware/software partitioning. J Supercomput 79(4):1204–1215

    MATH  Google Scholar 

  57. Wu JG, Srikanthan T, Zou GW (2008) New model and algorithm for hardware/software partitioning. J Comput Sci Technol 23(4):644–651

    MathSciNet  Google Scholar 

  58. Wu J, Srikanthan T, Lei T (2010) Efficient heuristic algorithms for path-based hardware/software partitioning. Math Comput Model 51(7):974–984

    MATH  Google Scholar 

  59. Arat P, Juhasz S, Mann Z, Orban A, Papp D (2003) Hardware–software partitioning in embedded system design. In: 2003 IEEE international symposium on intelligent signal processing, pp 197–202

  60. Arat P, Mann Z, Orban A (2005) Algorithmic aspects of hardware/software partitioning. ACM Trans Des Autom Electron Syst 10(1):136–156

    Google Scholar 

  61. Tahaee S, Jahangir A (2010) A polynomial algorithm for partitioning problems. ACM Trans Embed Comput Syst 9(4):34

    Google Scholar 

  62. Jiang Y, Zhang H, Jiao X, Song X, Hung WN, Gu M, Sun J (2012) Uncertain model and algorithm for hardware/software partitioning. In: 2012 IEEE computer society annual symposium on VLSI, IEEE, pp 243–248

  63. Wang R, Hung WN, Yang G, Song X (2016) Uncertainty model for configurable hardware/software and resource partitioning. IEEE Trans Comput 66(10):3217–3223

    MathSciNet  MATH  Google Scholar 

  64. Zuo W, Pouchet LN, Ayupov A, Kim T, Lin CW, Shiraishi S, Chen D (2017) Accurate high-level modeling and automated hardware/software co-design for effective SoC design space exploration. In: Design automation conference. ACM, p 78

  65. Kalavade AP (1995) System-level co-design of mixed hardware–software systems. Ph.D. dissertation. University of California, Berkeley. AAI9621207

  66. Niemann R, Marwedel P (1997) An algorithm for hardware/software partitioning using mixed integer linear programming. Des Autom Embed Syst 2(2):165–193

    Google Scholar 

  67. Banerjee S, Bozorgzadeh E, Dutt N (2006) Integrating physical constraints in HW/SW partitioning for architectures with partial dynamic reconfiguration. IEEE Trans Very Large Scale Integr 14(11):1189–1202

    Google Scholar 

  68. Ma Y, Liu J, Zhang C, Luk W (2014) HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. In: 32nd IEEE international conference on computer design, IEEE, pp 470–476

  69. Trindade A, Cordeiro L (2016) Applying SMT-based verification to hardware/software partitioning in embedded systems. Des Autom Embed Syst 20(1):1–19

    Google Scholar 

  70. Chatha K, Vemuri R (2002) Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans Very Large Scale Integr 10(3):193–208

    Google Scholar 

  71. Mann Z, Orban A, Arato P (2007) Finding optimal hardware/software partitions. Form Method Syst Des 31(3):241–263

    MATH  Google Scholar 

  72. Wu J, Chang B, Srikanthan T (2009) A hybrid branch-and-bound strategy for hardware/software partitioning. In: 8th IEEE/ACIS international conference on computer and information science, IEEE, pp 641–644

  73. Yuan M, Gu Z, He X, Liu X, Jiang L (2010) Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs. ACM Trans Des Autom Electron Syst 15(2):13

    Google Scholar 

  74. Gupta PK, De Micheli G (1993) Hardware–software co-synthesis for digital systems. IEEE Des Test Comput 10(3):29–41

    Google Scholar 

  75. Kalavade A, Lee E (1997) The extended partitioning problem: hardware/software mapping, scheduling, and implementation-bin selection. Des Autom Embed Syst 2(2):125–163

    Google Scholar 

  76. Kalavade A, Subrahmanyam P (1998) Hardware/software partitioning for multi-function systems. IEEE Trans Comput Aid Des Int 17(9):819–837

    Google Scholar 

  77. Wolf W (1997) An architectural co-synthesis algorithm for distributed, embedded computing systems. IEEE Trans Very Large Scale Integr 5(2):218–229

    Google Scholar 

  78. Boussaid I, Lepagnot J, Siarry P (2013) A survey on optimization metaheuristics. Inform Sci 237(237):82–117

    MathSciNet  MATH  Google Scholar 

  79. Zhang T, Zhao X, An X, Quan H, Lei Z (2017) Using blind optimization algorithm for hardware/software partitioning. IEEE Access 5:1353–1362

    Google Scholar 

  80. Saha D, Basu A, Mitra RS (1997) Hardware software partitioning using genetic algorithm. In: Proceedings of 10th international conference on VLSI design, IEEE, pp 155–160

  81. Srinivasan V, Radhakrishnan S, Vemuri R (1998) Hardware software partitioning with integrated hardware design space exploration. In: Proceedings of design, automation and test in Europe, IEEE, pp 28–35

  82. Zou Y, Zhuang Z, Chen H (2004) HW–SW partitioning based on genetic algorithm. In: 2004 IEEE congress on evolutionary computation. IEEE, pp 628–633

  83. Eles P, Peng Z, Kuchcinski K, Doboli A (1997) System level hardware/software partitioning based on simulated annealing and tabu search. Des Autom Embed Syst 2(1):5–32

    Google Scholar 

  84. Lopez-Vallejo M, Lopez JC (2003) On the hardware–software partitioning problem: system modeling and partitioning techniques. Acm Trans Des Autom Electron Syst 8(3):269–297

    Google Scholar 

  85. Banerjee S, Dutt N (2004) Efficient search space exploration for HW–SW partitioning. In: Proceedings of the 2nd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis. ACM, pp 122–127

  86. Garg K, Aung YL, Lam SK, Srikanthan T (2015) KnapSim-run-time efficient hardware–software partitioning technique for FPGAs. In: 28th IEEE international conference on system-on-chip, IEEE, pp 64–69

  87. Jemai M, Dimassi S, Ouni B, Mtibaa A (2017) A metaheuristic based on tabu search for hardware/software partitioning. Turk J Electr Eng Comput Sci 25(2):901–912

    Google Scholar 

  88. Wiangtong T, Cheung PYK, Luk W (2002) Comparing three heuristic search methods for functional partitioning in hardware–software codesign. Des Autom Embed Syst 6(4):425–449

    MATH  Google Scholar 

  89. Wu J, Srikanthan T, Jiao T (2008) Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design. Des Autom Embed Syst 12(4):345

    Google Scholar 

  90. Ashraf I, Ostadzadeh SA, Meeuws R, Bertels K (2013) Evaluation methodology for data communication-aware application partitioning. In: European conference on parallel processing. Springer, Berlin, pp 739–748

  91. Li L, Shi M (2008) Software–hardware partitioning strategy using hybrid genetic and tabu search. In: 2008 international conference on computer science and software engineering. IEEE, pp 83–86

  92. Li G, Feng J, Wang C, Wang J (2014) Hardware/software partitioning algorithm based on the combination of genetic algorithm and tabu search. Eng Rev 34(2):151–160

    MathSciNet  Google Scholar 

  93. Wang G, Gong W, Kastner R (2006) Application partitioning on programmable platforms using the ant colony optimization. J Embed Comput 2(1):119–136

    Google Scholar 

  94. Ferrandi F, Lanzi PL, Pilato C, Sciuto D, Tumeo A (2013) Ant colony optimization for mapping, scheduling and placing in reconfigurable systems. In: IEEE NASA/ESA conference on adaptive hardware and systems, IEEE, pp 47–54

  95. Koudil M, Benatchba K, Tarabet A, Sahraoui EB (2007) Using artificial bees to solve partitioning and scheduling problems in co-design. Appl Math Comput 186(2):1710–1722

    MathSciNet  MATH  Google Scholar 

  96. Abdelhalim M, Habib S (2011) An integrated high-level hardware/software partitioning methodology. Des Autom Embed Syst 15(1):19–50

    Google Scholar 

  97. Guoshuai L (2014) Improved hardware/software partitioning algorithm based on combination of PSO and TS. J Comput Inform Syst 10(14):5975–5985

    Google Scholar 

  98. Wu JG, Srikanthan T, Chen G (2010) Algorithmic aspects of hardware/software partitioning: 1D search algorithms. IEEE Trans Comput 59(4):532–544

    MathSciNet  MATH  Google Scholar 

  99. Wu JG, Wang P, Lam SK, Srikanthan T (2013) Efficient heuristic and tabu search for hardware/software partitioning. J Supercomput 66(1):118–134

    Google Scholar 

  100. Quan H, Zhang T, Liu Q, Guo J, Wang X, Hu R (2014) Comments on algorithmic aspects of hardware/software partitioning: 1D search algorithms. IEEE Trans Comput 63(4):1055–1056

    MathSciNet  MATH  Google Scholar 

  101. Mann Z, Orban A, Farkas A (2007) Evaluating the Kernighan–Lin heuristic for hardware/software partitioning. Int J Appl Math Comput Sci 17(2):249–267

    MathSciNet  MATH  Google Scholar 

  102. Abdelzaher TF, Kang GS (2000) Period-based load partitioning and assignment for large real-time applications. IEEE Trans Comput 49(1):81–87

    Google Scholar 

  103. Guo B, Wang D, Shen Y, Liu Z (2006) Hardware–software partitioning of real-time operating systems using Hopfield neural networks. Neurocomputing 69(16):2379–2384

    Google Scholar 

  104. Shen H, Sun C (2011) Achieving data consistency by contextualization in web-based collaborative applications. ACM Trans Internet Technol 10(4):13

    Google Scholar 

  105. Zhu H (2015) Role-based collaboration and E-CARGO: revisiting the developments of the last decade role-based collaboration (RBC). IEEE Syst Man Cybern Mag 1(3):27–36

    Google Scholar 

  106. Alba E, Luque G, Nesmachnow S (2013) Parallel metaheuristics: recent advances and new trends. Int Trans Oper Res 20(1):1–48

    MATH  Google Scholar 

  107. Farahani A, Kamal M, Salmani-Jelodar M (2006) Parallel genetic algorithm based HW/SW partitioning. In: International symposium on parallel computing in electrical engineering, pp 337–342

  108. Wu Y, Zhang H, Yang H (2009) Research on parallel HW/SW partitioning based on hybrid PSO algorithm. In: International conference on algorithms and architectures for parallel processing, pp 449–459

  109. Kromer P, Platos J, Snasel V (2014) Nature-inspired meta-heuristics on modern GPUs: state of the art and brief survey of selected algorithms. Int J Parallel Program 42(5):681–709

    Google Scholar 

  110. Tan Y, Ding K (2015) A survey on GPU-based implementation of swarm intelligence algorithms. IEEE Trans Cybern 46(9):2028–2041

    Google Scholar 

  111. Zhou Y, He F, Hou N, Qiu Y (2018) Parallel ant colony optimization on multi-core SIMD CPUs. Future Gener Comput Syst 79:473–487

    Google Scholar 

  112. Gepner P, Kowalik MF (2006) Multi-core processors: new way to achieve high system performance. In: International symposium on parallel computing in electrical engineering. IEEE, pp 9–13

  113. Fernando R (2004) GPGPU: general general-purpose purpose computation on GPUs. NVIDIA Developer Technology Group, Santa Clara

    Google Scholar 

  114. Goodnight N, Wang R, Humphreys G (2005) Computation on programmable graphics hardware. IEEE Comput Graph Appl 25(5):12–15

    Google Scholar 

  115. Manocha D (2005) General-purpose computations using graphics processors. Computer 38(8):85–88

    Google Scholar 

  116. Owens JD, Luebke D, Govindaraju N, Harris M, Kruger J, Lefohn AE, Purcell TJ (2007) A survey of general-purpose computation on graphics hardware. Comput Graph Forum 26(1):80–113

    Google Scholar 

  117. Owens JD, Houston M, Luebke D, Green S, Stone JE, Phillips JC (2008) GPU computing. Proc IEEE 96(5):879–899

    Google Scholar 

  118. Dagum L, Menon R (1998) OpenMP: an industry standard API for shared-memory programming. IEEE Comput Sci Eng 5(1):46–55

    Google Scholar 

  119. Sato M (2002) OpenMP: parallel programming API for shared memory multiprocessors and on-chip multiprocessors. In: Proceedings of the 15th international symposium on system synthesis. ACM, pp 109–111

  120. Bordoloi UD, Chakraborty S (2010) GPU-based acceleration of system-level design tasks. Int J Parallel Program 38(3–4):225–253

    MATH  Google Scholar 

  121. Nunna S, Bordoloi UD, Chakraborty S, Eles P, Peng Z (2011) Exploiting GPU on-chip shared memory for accelerating schedulability analysis. In: International symposium on electronic system design. IEEE, pp 147–152

  122. Yan X, He F, Chen Y (2017) A novel hardware/software partitioning method based on position disturbed particle swarm optimization with invasive weed optimization. J Comput Sci Technol 32(2):340–355

    MathSciNet  Google Scholar 

  123. Yan XH, He FZ, Hou N, Ai H (2018) An efficient particle swarm optimization for large-scale hardware/software co-design system. Int J Coop Inf Syst 27(01):1741001

    Google Scholar 

  124. Hou N, He F, Chen Y, Zhou Y (2016) An adaptive neighborhood taboo search on GPU for hardware/software co-design. In: IEEE 2016 international conference on computer supported cooperative work in design, IEEE, pp 239–244

  125. Hou N, He F, Zhou Y, Ai H (2017) A GPU-based tabu search for very large hardware/software partitioning with limited resource usage. J Adv Mech Des Syst Manuf 11(5):JAMDSM0060

    Google Scholar 

  126. Hou N, He F, Zhou Y, Chen Y (2019) An efficient GPU-based parallel tabu search algorithm for hardware/software co-design. Front Comput Sci 19:1–22

    Google Scholar 

  127. Hou N, He F, Zhou Y, Chen Y, Yan X (2018) A parallel genetic algorithm with dispersion correction for HW/SW partitioning on multi-core CPU and many-core GPU. IEEE Access 6:883–898

    Google Scholar 

  128. LeCun Y, Bengio Y, Hinton G (2015) Deep learning. Nature 521(7553):436

    Google Scholar 

  129. Zhang S, He F, Ren W, Yao J (2018) Joint learning of image detail and transmission map for single image dehazing. Visual Comput. https://doi.org/10.1007/s00371-018-1612-9

    Google Scholar 

  130. Kahng AB (2018) Machine learning applications in physical design: recent results and directions. In: Proceedings of the 2018 international symposium on physical design. ACM, pp 68–73

  131. Danglade F, Pernot JP, Veron P (2014) On the use of machine learning to defeature CAD models for simulation. Comput Aid Des Appl 11(3):358–368

    Google Scholar 

  132. McMahon C (2017) Open issues in design informatics. Mach Dyn Res 41(2):141–151

    Google Scholar 

  133. Wang K, Savva M, Chang AX, Ritchie D (2018) Deep convolutional priors for indoor scene synthesis. ACM Trans Graph 37(4):70

    Google Scholar 

  134. Tanaka M, Takamiya Y, Tsubota N, Asanuma S, Iwama K (2017) Reconstruction of solid models from sketches including curves with inductive learning technique. Comput Aid Des Appl 14(5):632–641

    Google Scholar 

  135. Zhou Y, He F, Qiu Y (2016) Optimization of parallel iterated local search algorithms on graphics processing unit. J Supercomput 72(6):2394–2416

    Google Scholar 

  136. Zhou Y, He F, Qiu Y (2017) Dynamic strategy based parallel ant colony optimization on GPUs for TSP. Sci China Inf Sci 60(6):068102

    Google Scholar 

  137. Rios E, Ochi LS, Boeres C, Coelho VN, Coelho IM, Farias R (2018) Exploring parallel multi-GPU local search strategies in a metaheuristic framework. J Parallel Distrib Comput 111:39–55

    Google Scholar 

  138. Ferreiro AM, Garcia JA, Lopez-Salas JG, Vazquez C (2013) An efficient implementation of parallel simulated annealing algorithm in GPUs. J Glob Optim 57(3):863–890

    MathSciNet  MATH  Google Scholar 

  139. Chen Z, Yeo CK, Lee BS, Lau CT, Jin Y (2018) Evolutionary multi-objective optimization based ensemble autoencoders for image outlier detection. Neurocomputing 309:192–200

    Google Scholar 

  140. Li HR, He FZ, Yan XH (2019) IBEA-SVM: an indicator-based evolutionary algorithm based on pre-selection with classification guided by SVM. Appl Math J Chin Univ Ser B 34(1):1–26

    MathSciNet  Google Scholar 

  141. Wang H, Jin Y, Sun C, Doherty J (2018) Offline data-driven evolutionary optimization using selective surrogate ensembles. IEEE Trans Cybern. https://doi.org/10.1109/TEVC.2018.2834881

    Google Scholar 

  142. Jin Y, Wang H, Chugh T, Guo D, Miettinen K (2018) Data-driven evolutionary optimization: an overview and case studies. IEEE Trans Cybern. https://doi.org/10.1109/TEVC.2018.2869001

    Google Scholar 

  143. Wang H, Jin Y (2018) A random forest-assisted evolutionary algorithm for data-driven constrained multiobjective combinatorial optimization of trauma systems. IEEE Trans Cybern. https://doi.org/10.1109/TCYB.2018.2869674

    Google Scholar 

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Acknowledgements

Funding was provided by National Natural Science Foundation of China (Grant No. 61472289) and National Key Research and Development Project (Grant No. 2016YFC0106305).

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  1. School of Computer Science, Wuhan University, Wuhan, 430072, Hubei, China

    Neng Hou, Xiaohu Yan & Fazhi He

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  2. Xiaohu Yan
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  3. Fazhi He
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Correspondence to Fazhi He.

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Hou, N., Yan, X. & He, F. A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design. Des Autom Embed Syst 23, 57–77 (2019). https://doi.org/10.1007/s10617-019-09220-7

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