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Trace-driven and processing time extensions for Noxim simulator

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Abstract

Simulation is one of the main tools used to analyze and test new proposals in the Network-on-Chip field. Several simulators can be found in the literature, among them the Noxim simulator stands out. It is being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the system and its features. The correct workload can lead to rapid and efficient system development, while the wrong one may compromise the entire system evaluation. To ensure a more realistic simulation, simulators usually relies on real workloads by using a trace-driven approach. Although Noxim provides a simple support for input traces, it is very limited to a general behavior of the system, accepting only a generic injection rate parameter over time. Another important part of the simulator is the ability to consider the Processing Elements processing time. We propose in this paper an extension of the Noxim simulator to address these issues. Consequently, results are more realistic and may be possible to predict the total execution time very accurately. This extension is demonstrated and evaluated using the NAS-NPB workload.

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Notes

  1. The file /mpe2-2.4.7/src/wrappers/src/trace_mpi_core.c was instrumented to trace all the communication messages sent by the MPI.

References

  1. Abad P, Prieto P, Menezo LG, Colaso A, Puente V, Gregorio JA (2012) Topaz: an open-source interconnection network simulator for chip multiprocessors and supercomputers. In: 2012 IEEE/ACM sixth international symposium on networks-on-chip, pp 99–106. https://doi.org/10.1109/NOCS.2012.19

  2. Agarwal N, Krishna T, Peh LS, Jha NK (2009) Garnet: A detailed on-chip network model inside a full-system simulator. In: 2009 IEEE international symposium on performance analysis of systems and software, pp 33–42. https://doi.org/10.1109/ISPASS.2009.4919636

  3. Alliance W (2014) Wi-fi alliance wigig wireless bus extension technical specification. www.wi-fi.org. Accessed 10 Sept 2016

  4. Bailey D, Harris T, Saphir W, van der Wijngaart R, Woo A, Yarrow M (1995) The NAS parallel benchmarks 2.0. Tech. rep., NAS Technical Report, NAS-95-020

  5. Ben-Itzhak Y, Zahavi E, Cidon I, Kolodny A (2011) Nocs simulation framework for omnet++. In: Proceedings of the fifth ACM/IEEE international symposium, pp 265–266. https://doi.org/10.1145/1999946.1999993

  6. Ben-Itzhak Y, Zahavi E, Cidon I, Kolodny A (2012) Hnocs: modular open-source simulator for heterogeneous nocs. In: 2012 international conference on embedded computer systems (SAMOS), pp 51–57. https://doi.org/10.1109/SAMOS.2012.6404157

  7. Benini L, Micheli GD (2002) Networks on chips: a new soc paradigm. Computer 35(1):70–78. https://doi.org/10.1109/2.976921

    Article  Google Scholar 

  8. Binkert N, Beckmann B, Black G, Reinhardt SK, Saidi A, Basu A, Hestness J, Hower DR, Krishna T, Sardashti S, Sen R, Sewell K, Shoaib M, Vaish N, Hill MD, Wood DA (2011) The gem5 simulator. SIGARCH Comput Archit N 39(2):1–7. https://doi.org/10.1145/2024716.2024718

    Article  Google Scholar 

  9. Catania V, Mineo A, Monteleone S, Palesi M, Patti D (2015) Noxim: An open, extensible and cycle-accurate network on chip simulator. In: 2015 IEEE 26th international conference on application-specific systems, architectures and processors (ASAP), pp 162–163. https://doi.org/10.1109/ASAP.2015.7245728

  10. da Cruz EHM, Alves MAZ, Carissimi A, Navaux POA, Ribeiro CP, Mehaut JF (2011) Using memory access traces to map threads and data on hierarchical multi-core platforms. In: 2011 IEEE international symposium on parallel and distributed processing workshops and Ph.d. Forum, pp 551–558. https://doi.org/10.1109/IPDPS.2011.197

  11. Deb S, Ganguly A, Pande PP, Belzer B, Heo D (2012) Wireless noc as interconnection backbone for multicore chips: promises and challenges. IEEE J Emerg Sel Top Circuits Syst 2(2):228–239. https://doi.org/10.1109/JETCAS.2012.2193835

    Article  Google Scholar 

  12. Diener M, Cruz EH, Pilla LL, Dupros F, Navaux PO (2015) Characterizing communication and page usage of parallel applications for thread and data mapping. Perform Eval 88–89:18–36. https://doi.org/10.1016/j.peva.2015.03.001

    Article  Google Scholar 

  13. de Freitas HC, Schnorr LM, Alves MAZ, Navaux POA (2010) Impact of parallel workloads on noc architecture design. In: 2010 18th euromicro conference on parallel, distributed and network-based processing, pp 551–555. https://doi.org/10.1109/PDP.2010.53

  14. Hansen CJ (2011) WiGiG: multi-gigabit wireless communications in the 60 GHz band. IEEE Wirel Commun 18(6):6–7. https://doi.org/10.1109/MWC.2011.6108325

    Article  Google Scholar 

  15. Hestness J, Grot B, Keckler SW (2010) Netrace: Dependency-driven trace-based network-on-chip simulation. In: Proceedings of the third international workshop on network on chip architectures, NoCArc ’10, ACM, New York, NY, pp 31–36. https://doi.org/10.1145/1921249.1921258

  16. Hossain H, Ahmed M, Al-Nayeem A, Islam TZ, Akbar MM (2007) Gnocsim–a general purpose simulator for network-on-chip. In: International conference on information and communication technology

  17. InfiniBand Trade Association and others: InfiniBand Architecture Specification, release 1.0 (2000). www.infinibandta.org. Accessed 23 Oct 2016

  18. Jain Lavina, Al-Hashimi BM, Gaur MS, Laxmi V, Narayanan A (2007) NIRGAM: a simulator for NoC interconnect routing and application modeling. In: Design, automation and test in Europe conference

  19. Jain Raj (1990) The art of computer systems performance analysis: techniques for experimental design, measurement, simulation, and modeling. Wiley, London

    Google Scholar 

  20. Jiang N, Balfour J, Becker DU, Towles B, Dally WJ, Michelogiannakis G, Kim J (2013) A detailed and flexible cycle-accurate network-on-chip simulator. In: 2013 IEEE international symposium on performance analysis of systems and software (ISPASS), pp 86–96. https://doi.org/10.1109/ISPASS.2013.6557149

  21. Kurimoto Y, Fukutsuka Y, Taniguchi I, Tomiyama H (2013) A hardware/software cosimulator for network-on-chip. In: 2013 international SoC design conference (ISOCC), pp 172–175. https://doi.org/10.1109/ISOCC.2013.6863964

  22. LAN/MAN Standards Committee: IEEE Standard for Ethernet. IEEE Std 802.3-2015 (2016)

  23. Lis M, Shim KS, Cho MH, Ren P, Khan O, Devadas S (2010) DARSIM: a parallel cycle-level NoC simulator. In: Workshop on modeling, benchmarking and simulation

  24. Lu Z, Thid R, Millberg M, Jantsch A (2005) NNSE: nostrum network-on-chip simulation environment. In: Swedish system-on-chip conference

  25. Micheli GD, Benini L (2017) Networks on chips: 15 years later. Computer 50(5):10–11. https://doi.org/10.1109/MC.2017.140

    Article  Google Scholar 

  26. Nakajima K, Kurebayashi S, Fukutsuka Y, Hieda T, Taniguchi I, Tomiyama H, Takada H (2013) Naxim: a fast and retargetable network-on-chip simulator with qemu and systemc. Int J Netw Comput 3(2):217–227. https://doi.org/10.15803/ijnc.3.2_217

  27. Peng IB, Markidis S, Gioiosa R, Kestor G, Laure E (2017) Mpi streams for hpc applications. N Front High Perform Comput Big Data 30:75

    Google Scholar 

  28. Pires ILP, Alves MAZ, Albini LCP (2017) Trace-driven extension for noxim simulator. In: 2017 VII Brazilian symposium on computing systems engineering (SBESC), pp 102–108. https://doi.org/10.1109/SBESC.2017.20

  29. Ren P, Lis M, Cho MH, Shim KS, Fletcher CW, Khan O, Zheng N, Devadas S (2012) Hornet: a cycle-level multicore simulator. IEEE Trans Comput-Aided Des Integr Circuit Syst 31(6):890–903. https://doi.org/10.1109/TCAD.2012.2184760

    Article  Google Scholar 

  30. Riley George F, Henderson Thomas R (2010) The ns-3 network simulator. Springer, Berlin

    Google Scholar 

  31. Shamim MS, Mansoor N, Narde RS, Kothandapani V, Ganguly A, Venkataraman J (2017) A wireless interconnection framework for seamless inter and intra-chip communication in multichip systems. IEEE Trans Comput 66(3):389–402. https://doi.org/10.1109/TC.2016.2605093

    Article  MathSciNet  MATH  Google Scholar 

  32. Shamim MS, Muralidharan J, Ganguly A (2015) An interconnection architecture for seamless inter and intra-chip communication using wireless links. In: Proceedings of the 9th international symposium on networks-on-chip, NOCS ’15, ACM, New York, NY, USA, pp 2:1–2:8. https://doi.org/10.1145/2786572.2786581

  33. Swaminathan K, Thakyal D, Nambiar SG, Lakshminarayanan G, Ko SB (2014) Enhanced noxim simulator for performance evaluation of network on chip topologies. In: 2014 recent advances in engineering and computational sciences (RAECS), pp 1–5. https://doi.org/10.1109/RAECS.2014.6799570

  34. VanderWijngaart RF, Haopiang J (2003) NAS Parallel benchmarks, multi-zone versions, NAS Technical Report

  35. Wang C, Hu WH, Bagherzadeh N (2011) A wireless network-on-chip design for multicore platforms. In: 2011 19th international euromicro conference on parallel, distributed and network-based processing, pp 409–416. https://doi.org/10.1109/PDP.2011.37

  36. WiFi Alliance: 60 GHz Technical Specification v1.0 (2017). www.wi-fi.org. Accessed 10 Sept 2016

  37. Wilton SJE, Jouppi NP (1996) Cacti: an enhanced cache access and cycle time model. IEEE J Solid-State Circuits 31(5):677–688. https://doi.org/10.1109/4.509850

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Informatics, Federal University of Paraná (UFPR), Curitiba, Brazil

    Ivan Luiz Pedroso Pires, Marco Antonio Zanata Alves & Luiz Carlos Pessoa Albini

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  1. Ivan Luiz Pedroso Pires
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  2. Marco Antonio Zanata Alves
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  3. Luiz Carlos Pessoa Albini
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Correspondence to Luiz Carlos Pessoa Albini.

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This work was partially supported by CNPq and CAPES.

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Pires, I.L.P., Alves, M.A.Z. & Albini, L.C.P. Trace-driven and processing time extensions for Noxim simulator. Des Autom Embed Syst 23, 41–55 (2019). https://doi.org/10.1007/s10617-018-09218-7

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