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Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications

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Abstract

The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson (multiplicative) method and it supports all IEEE rounding modes with a latency of 15 cycles. The iterative NR computations are performed by using FP multiplier and FP adder. The key module of FP multiplier for calculating mantissa part is UT multiplier. It’s an ancient Vedic multiplication technique used from few centuries back for doing fast multiplications. We implemented two UT multipliers: one using carry look-ahead adders and another one using carry save adders. The results show that, the proposed architectures have 12% better precision with 24% high throughput than existing algorithms, at the cost of high on-chip power. The inputs to the divider are represented in IEEE-754 standard. The design uses Xilinx Vivado software and it is implemented on Virtex7 FPGA.

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Authors and Affiliations

  1. Department of Electronics and Communications Engineering, CEG, Anna University, Chennai, India

    C. R. S. Hanuman, J. Kamala & A. R. Aruna

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  1. C. R. S. Hanuman
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  2. J. Kamala
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  3. A. R. Aruna
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Correspondence to C. R. S. Hanuman.

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Hanuman, C.R.S., Kamala, J. & Aruna, A.R. Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications. Des Autom Embed Syst 24, 111–125 (2020). https://doi.org/10.1007/s10617-019-09225-2

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