Elsevier

Theoretical Computer Science

Volume 889, 8 October 2021, Pages 1-13
Theoretical Computer Science

Succinct certification of monotone circuits

https://doi.org/10.1016/j.tcs.2021.07.032Get rights and content

Abstract

Monotone Boolean circuits are circuits where each gate is either an AND gate or an OR gate. In other words, negation gates are not allowed on monotone circuits. This class of circuits has sparked the attention of researchers working in several subfields of combinatorics and complexity theory. In this work, we consider the notion of certification-width of a monotone Boolean circuit, a complexity measure that intuitively quantifies the minimum number of edges that need to be traversed by a minimal set of positive weight inputs in order to certify that a given circuit is satisfied. We call the problem of computing this invariant as Succinct Monotone Circuit Certification (SMCC). We prove that SMCC is NP-complete even when the input monotone circuit is planar. Subsequently, we show that k-SMCC, the problem parameterized by the size of the solution, is W[1]-hard, but still in W[P]. In contrast, we show that k-SMCC is fixed-parameter tractable when restricted to monotone circuits of bounded genus.

Introduction

Boolean circuits are one of the earliest combinatorial formalisms for the representation of Boolean functions. Besides being a fundamental object of study in classical complexity theory, Boolean circuits also play a central role in the field of parameterized complexity [10]. More specifically, while the satisfiability problem for general Boolean circuits can be used to define the class NP, the satisfiability problem for Boolean circuits of bounded weft can be used to define the levels of the W-hierarchy [10]. An important, and well-studied, subclass of Boolean circuits is the class of monotone Boolean circuits, i.e., circuits where only AND and OR gates are allowed. While the standard satisfiability problem for monotone Boolean circuits is trivial, since the all-ones vector is always a satisfying assignment, some weighted versions of satisfiability problems are still interesting in this setting. One of these problems is the Weighted Monotone Circuit Satisfiability (WMCS) problem, where we are given a monotone Boolean circuit C as input, and the goal is to find a minimum-weight satisfying assignment for the inputs of C [6], [16], [19]. The WMCS is particularly relevant in the field of circuit design, since the minimum number of inputs necessary to make a monotone circuit evaluate to true is a parameter that is often taken into consideration [18].

In this paper, we deal with the notion of succinct certificates for monotone Boolean circuits. Given a monotone circuit C, a succinct certificate for C is a connected sub-circuit of C with a minimal set of edges that is sufficient to ensure that C is satisfiable. Just like circuit size and circuit depth, the minimum size of a succinct certificate is an interesting complexity measure. Additionally, a succinct certificate may be seen as a minimal map to be followed by a satisfying assignment. This map may find applications in the field of circuit design and may be used as a way of representing solutions to problems modeled through monotone circuits. In the literature similar structures are known as accepting subtree [33], positive proof [9], and proving circuit [21].

We study the complexity of computing the size of a minimum succinct certificate of a given monotone circuit C. We call this invariant the certification-width of C, and name the problem of computing the value of this invariant as the Succinct Monotone Circuit Certification (SMCC) problem. The problem under consideration is both of theoretical and practical relevance. From a theoretic perspective, the minimum size of a succinct certificate naturally gives information about the complexity of a circuit. Therefore, determining the underlying structure that makes SMCC (fixed-parameter) tractable is interesting from the perspective of complexity theory. From a practical perspective, SMCC can be applied in many problem-reduction representations [22], since monotone circuits can be seen as unweighted And/Or graphs [28], [29].

The notion of planarity is well-explored in graph theory and has significant relevance in the field of circuit analysis. In particular, VLSI (Very Large-Scale Integration) circuits, which are widely applied in electronics and engineering, are typically modeled by planar graphs. In addition, there are several studies on circuits and satisfiability problems defined on certain structures that are planar or that satisfy certain structural properties (see [2], [4], [16], [17], [18], [19], [27], [30], [31]).

We show that SMCC is NP-hard when the input monotone circuit is planar, and it is W[1]-hard, but in W[P], when parameterized by solution size. Subsequently, we present a polynomial-time algorithm that takes a monotone circuit as input and either solves the instance or bounds the diameter of the input; then using the notion of contraction obstructions for treewidth we are able to conclude that the treewidth of the resulting circuit is bounded by k+g, where k is the solution size and g is the genus of the input circuit. Thus, by using such a win/win approach and applying a dynamic programming algorithm we solve SMCC in FPT time when parameterized by k+g. This result also implies that SMCC can be solved in time 2O(k)n+m on planar circuits.

An extended abstract of this paper has been presented in COCOON 2020 [1].

Section snippets

Preliminaries

We use standard graph-theoretic and parameterized complexity notation, and we refer the reader to [10], [7] for any undefined notation.

A Boolean circuit is a combinatorial model for the representation of Boolean functions. We formalize the notion of a Boolean circuit according to Definition 1. In general, a circuit can have multiples outputs. Nevertheless, for convenience, we will adopt the following definition.

Definition 1

A Boolean circuit is a directed acyclic graph C(V,E) having only one sink, where the

NP-completeness on planar circuits

Now, we dedicate our attention to SMCC restricted to planar circuits. Clearly, SMCC is in NP. Next, we show its NP-hardness. For that, we will use a reduction from Planar Vertex Cover.

Theorem 1

SMCC is NP-complete even restricted to planar circuits.

Proof

Given a circuit C and an integer k, forming an instance of SMCC, a connected subgraph of C having at most k edges and satisfying Definition 6 can be seen as a certificate for the “yes” answer of this instance. Since it is easy to verify in polynomial time the

Parameterized complexity

In this section, we analyze the parameterized complexity of SMCC. We refer the reader to [10], [7] for basic background on parameterized complexity, and we recall here only some basic definitions.

A parameterized problem is a decision problem whose instances are pairs (x,k)Σ×N, where k is called the parameter. A parameterized problem is fixed-parameter tractable (FPT) if there exists an algorithm A, a computable function f, and a constant c such that given an instance I=(x,k), A (called an FPT

Conclusions

Although several works deal with complexity measures closely related to the notion of a succinct certificate, most of the literature results focus on discovering lower and upper bounds for these measures and characterizing related complexity classes. In this paper, we address another direction, we introduce the Succinct Monotone Circuit Certification problem and investigate its time complexity. We show that SMCC is NP-complete even when the input monotone circuit is planar. Regarding

Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgement

We acknowledge support from FAPERJ (E-26/203.272/2017), CAPES (Finance Code: 001), CNPq (303726/2017-2, 309832/2020-9), Research Council of Norway (288761), and from the Sigma2 network (NN9535K).

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