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Simplified introduction of power intent into a register-transfer level model

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Abstract

In highly-integrated electronic circuits designs, power reduction must be properly addressed. The standardized ways of power-intent specification are unbearable in modern complex designs, since they extensively prolong the time-to-market of products. In this article, we propose a simplified method of designing energy-efficient systems at the register-transfer level, which is fully compatible with the existing design flow and industrial automation tools. The power-intent specification is abstract enough to be easily integrated into the HDL model, which also simplifies its maintainability. A connection to later design-flow stages (i.e. lower abstraction levels) is achieved by automated synthesis, which translates the simplified specification into the standard means, supported by the existing professional design-automation tools. The benefit of the proposed design method is speed-up of the development process, reduced number of possible power-intent errors, and easier energy-efficient systems design. Such design can be utilized by all designers, even those, which were unable to utilize the standard means due to high complexity. The experiments using 10 000 power-intent specification samples have shown that the proposed specification method is approximately 23-times less complex (in terms of lines of code) than the standard method. Moreover, it is able to achieve the same power-consumption reduction, while requiring much less designer effort.

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Notes

  1. Power sources are specified as a command line arguments, as they have no real backing in the HDL model.

  2. For an example in Fig. 6, the order is: NORMAL, \({C_{1}P_{2}}, {C_{1}P_{3}}, {C_{2}P_{2} (internal)}, {2}\), \({C_{2}P_{3}}, {C_{3}P_{3} (internal)}\), and 3.

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Acknowledgements

This publication has been written thanks to support of the Ministry of Education, Science, Research and Sport of the Slovak Republic (Incentives for Research and Development, Grant No.: 2018/14427:1-26C0) and the ESET Research Centre.

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Authors and Affiliations

  1. Slovak University of Technology in Bratislava, Bratislava, Slovakia

    Matej Groma & Dominik Macko

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  1. Matej Groma
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  2. Dominik Macko
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Correspondence to Dominik Macko.

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Appendix A: Example model

Appendix A: Example model

The full source code of the converter module with the simplified power intent specification used in the experiments is provided in Listing 1. The power intent using the standard means resulted from the synthesis using the implemented tool is provided in Listing 2 for the Verilog output and in Listing 3 for the UPF output.

figure a
figure b
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Groma, M., Macko, D. Simplified introduction of power intent into a register-transfer level model. Des Autom Embed Syst 25, 297–324 (2021). https://doi.org/10.1007/s10617-021-09254-w

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