Skip to main content

Advertisement

SpringerLink
Log in

LMM: A Fixed-Point Linear Mapping Based Approximate Multiplier for IoT

  • Regular Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

The development of IoT (Internet of Things) calls for circuit designs with energy and area efficiency for edge devices. Approximate computing which trades unnecessary computation precision for hardware cost savings is a promising direction for error-tolerant applications. Multipliers, as frequently invoked basic modules which consume non-trivial hardware costs, have been introduced approximation to achieve distinct energy and area savings for data-intensive applications. In this paper, we propose a fixed-point approximate multiplier that employs a linear mapping technique, which enables the configurability of approximation levels and the unbiasedness of computation errors. We then introduce a dynamic truncation method into the proposed multiplier design to cover a wider and more fine-grained configuration range of approximation for more flexible hardware cost savings. In addition, a novel normalization module is proposed for the required shifting operations, which balances the occupied area and the critical path delay compared with normal shifters. The introduced errors of our proposed design are analyzed and expressed by formulas which are validated by experimental results. Experimental evaluations show that compared with accurate multipliers, our proposed approximate multiplier design provides maximum area and power savings up to 49.70% and 66.39% respectively with acceptable computation errors.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

References

  1. Atzori L, Iera A, Morabito G. The Internet of Things: A survey. Computer Networks, 2010, 54(15): 2787–2805. https://doi.org/10.1016/j.comnet.2010.05.010.

    Article  MATH  Google Scholar 

  2. Zhuo C, Luo S H, Gan H L, Hu J, Shi Z G. Noise-aware DVFS for efficient transitions on battery-powered IoT devices. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(7): 1498–1510. https://doi.org/10.1109/tcad.2019.2917844.

    Article  Google Scholar 

  3. Wen C Y, Dong X, Chen B X, Tida U R, Shi Y Y, Zhuo C. Magnetic core TSV-inductor design and optimization for on-chip DC-DC converter. ACM Trans. Design Automation of Electronic Systems, 2022, 27(5): Article No. 52. https://doi.org/10.1145/3507700.

  4. Gupta V, Mohapatra D, Park S P, Raghunathan A, Roy K. IMPACT: IMPrecise adders for low-power approximate computing. In Proc. the 2011 IEEE/ACM International Symposium on Low Power Electronics and Design, Aug. 2011, pp.409–414. https://doi.org/10.1109/ISLPED.2011.5993675.

  5. Han J, Orshansky M. Approximate computing: An emerging paradigm for energy-efficient design. In Proc. the 18th IEEE European Test Symposium, May 2013. https://doi.org/10.1109/ETS.2013.6569370.

  6. Imani M, Rahimi A, Rosing T S. Resistive configurable associative memory for approximate computing. In Proc. the 2016 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2016, pp.1327–1332. https://doi.org/10.3850/9783981537079_0454.

  7. Liu W Q, Lombardi F, Shulte M. A retrospective and prospective view of approximate computing. Proceedings of the IEEE, 2020, 108(3): 394–399. https://doi.org/10.1109/jproc.2020.2975695.

    Article  Google Scholar 

  8. Venkataramani S, Chippa V K, Chakradhar S T, Roy K, Raghunathan A. Quality programmable vector processors for approximate computing. In Proc. the 46th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2013. 10.1145/2540708.2540710.

  9. Deng J N, Shi Z G, Zhuo C. Energy-efficient real-time UAV object detection on embedded platforms. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(10): 3123–3127. https://doi.org/10.1109/tcad.2019.2957724.

    Article  Google Scholar 

  10. Mitchell J N. Computer multiplication and division using binary logarithms. IRE Trans. Electronic Computers, 1962, EC-11(4): 512–517. https://doi.org/10.1109/tec.1962.5219391.

    Article  MathSciNet  MATH  Google Scholar 

  11. Lim Y C. Single-precision multiplier with reduced circuit complexity for signal processing applications. IEEE Trans. Computers, 1992, 41(10): 1333–1336. https://doi.org/10.1109/12.166611.

    Article  Google Scholar 

  12. Schulte M J, Swartzlander E E. Truncated multiplication with correction constant. In Proc. the 1993 IEEE Workshop on VLSI Signal Processing, Oct. 1993, pp.388–396. https://doi.org/10.1109/vlsisp.1993.404467.

  13. Ansari M S, Cockburn B F, Han J. An improved logarithmic multiplier for energy-efficient neural computing. IEEE Trans. Computers, 2020, 70(4): 614–625. https://doi.org/10.1109/tc.2020.2992113.

    Article  MathSciNet  MATH  Google Scholar 

  14. Liu W Q, Xu J H, Wang D Y, Wang C H, Montuschi P, Lombardi F. Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications. IEEE Trans. Circuits and Systems I: Regular Papers, 2018, 65(9): 2856–2868. https://doi.org/10.1109/tcsi.2018.2792902.

    Article  Google Scholar 

  15. Esposito D, Strollo A G M, Napoli E, De Caro D, Petra N. Approximate multipliers based on new approximate compressors. IEEE Trans. Circuits and Systems I: Regular Papers, 2018, 65(12): 4169–4182. https://doi.org/10.1109/tcsi.2018.2839266.

    Article  Google Scholar 

  16. Ha M, Lee S. Multipliers with approximate 4-2 compressors and error recovery modules. IEEE Embedded Systems Letters, 2018, 10(1): 6–9. https://doi.org/10.1109/les.2017.2746084.

    Article  Google Scholar 

  17. Hashemi S, Bahar R I, Reda S. DRUM: A dynamic range unbiased multiplier for approximate applications. In Proc. the 2015 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2015, pp.418–425. https://doi.org/10.1109/iccad.2015.7372600.

  18. Kulkarni P, Gupta P, Ercegovac M. Trading accuracy for power with an underdesigned multiplier architecture. In Proc. the 24th International Conference on VLSI Design, Jan. 2011, pp.346–351. https://doi.org/10.1109/vlsid.2011.51.

  19. Narayanamoorthy S, Moghaddam H A, Liu Z H, Park T, Kim N S. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2015, 23(6): 1180–1184. https://doi.org/10.1109/tvlsi.2014.2333366.

    Article  Google Scholar 

  20. Tung C W, Huang S H. Low-power high-accuracy approximate multiplier using approximate high-order compressors. In Proc. the 2nd International Conference on Communication Engineering and Technology, Apr. 2019, pp.163–167. https://doi.org/10.1109/iccet.2019.8726875.

  21. Venkatachalam S, Ko S B. Design of power and area efficient approximate multipliers. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2017, 25(5): 1782–1786. https://doi.org/10.1109/tvlsi.2016.2643639.

    Article  Google Scholar 

  22. George J, Marr B, Akgul B E S, Palem K V. Probabilistic arithmetic and energy efficient embedded signal processing. In Proc. the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Oct. 2006, pp.158–168. https://doi.org/10.1145/1176760.1176781.

  23. Schlachter J, Camus V, Enz C, Palem K V. Automatic generation of inexact digital circuits by gate-level pruning. In Proc. the 2015 IEEE International Symposium on Circuits and Systems, May 2015, pp.173–176. https://doi.org/10.1109/iscas.2015.7168598.

  24. Chen C T, Qian W K, Imani M, Yin X Z, Zhuo C. PAM: A piecewise-linearly-approximated floating-point multiplier with unbiasedness and configurability. IEEE Trans. Computers, 2022, 71(10): 2473–2486. https://doi.org/10.1109/tc.2021.3131850.

    Article  Google Scholar 

  25. Oklobdzija V G. An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 1994, 2(1): 124–128. https://doi.org/10.1109/92.273153.

    Article  Google Scholar 

  26. Wallace C S. A suggestion for a fast multiplier. IEEE Trans. Electronic Computers, 1964, EC-13 (1): 14–17. https://doi.org/10.1109/pgec.1964.263830.

    Article  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China

    Ying Wu, Chen-Yi Wen, Xun-Zhao Yin & Cheng Zhuo

  2. Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province, Hangzhou, 310027, China

    Cheng Zhuo

Authors
  1. Ying Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Chen-Yi Wen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Xun-Zhao Yin
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Cheng Zhuo
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Cheng Zhuo.

Supplementary Information

ESM 1

(PDF 145 kb)

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wu, Y., Wen, CY., Yin, XZ. et al. LMM: A Fixed-Point Linear Mapping Based Approximate Multiplier for IoT. J. Comput. Sci. Technol. 38, 298–308 (2023). https://doi.org/10.1007/s11390-023-2572-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-023-2572-8

Keywords

Search

Navigation