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Run-time reconfigurable nanomagnetic logic gates and comparator designs using very high-permeability material

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Abstract

Nanomagnetic logic is a recent technology used in electronic devices and systems. The current challenge in circuit miniaturization has prompted a move away from the traditional metal-oxide-semiconductor technology. Nanomagnetic logic-based devices have no leakage current, and they are also non-volatile. In this paper, we propose run-time reconfigurable layout designs for the logic gates, and to show the applicability of the logic gates, we implement a single-bit comparator design. For the logic gate designs, we use slant-edge nanomagnets of different shapes as inputs. The proposed layout designs are verified using the MuMax3 micro-magnetic simulation tool, and results are compared with a previous approach. The implementation of a single-bit comparator design can significantly reduce the number of nanodots required, typically by \(\sim\)50–80%, as well as the area occupancy, which can be reduced by \(\sim\)56–99%.

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Authors and Affiliations

  1. School of VLSI Design and Embedded System, National Institute of Technology, Kurukshetra, Haryana, 136119, India

    Vineet Jaiswal

  2. Department of Electronics and Communication Engineering, National Institute of Technology, Kurukshetra, Haryana, 136119, India

    Trailokya Nath Sasamal

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  1. Vineet Jaiswal
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Contributions

VJ and TNS were involved in the design of the layout, simulation studies, and analysis, and they both contributed to the writing of the manuscript. VJ initially drafted the manuscript, which was subsequently improved by both VJ and TNS. All authors have reviewed and given their approval for the final version of the manuscript.

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Correspondence to Vineet Jaiswal.

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Jaiswal, V., Sasamal, T.N. Run-time reconfigurable nanomagnetic logic gates and comparator designs using very high-permeability material. J Comput Electron 22, 1748–1759 (2023). https://doi.org/10.1007/s10825-023-02105-w

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