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Analysis and codesign of electronic–photonic integrated circuit hardware accelerator for machine learning application

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Abstract

Innovations in deep learning technology have recently focused on photonics as a computing medium. Integrating an electronic and photonic approach is the main focus of this work utilizing various photonic architectures for machine learning applications. The speed, power, and reduced footprint of these photonic hardware accelerators (HA) are expected to greatly enhance inference. In this work, we propose a hybrid design of an electronic and photonic integrated circuit (EPIC) hardware accelerator (EPICHA), an electronic–photonic framework that uses architecture-level integrations for better performance. The proposed EPICHA has a systematic structure of reconfigurable directional couplers (RDCs) to build a scalable, efficient machine learning accelerator for inference applications. In the simulation framework, the input and output layers of a fully integrated photonic neural network use the same integrated photodetector and RDC technology as the activation function. Our system only compromises on latency because of the electro–optical conversion process and the hand-off between the electronic and photonic domains. Insertion losses in photonic components have a small negative impact on accuracy when using more deep learning stages. Our proposed EPICHA utilizes coherent operation, and hence uses a single wavelength of λ = 1550 nm. We used the interoperability feature of the Ansys Lumerical MODE, DEVICE, and INTERCONNECT tools for component modeling in the photonic and electrical domain, and circuit-level simulation using S-parameters with MATLAB. The electronic component acts as the controller, which generates the required analog voltage control signals for each RDC present in the photonic processing engine. We employed MathWorks MATLAB 2022b for the classification of handwritten digits from the MNIST database; the proposed coherent EPICHA achieved accuracy of 94%.

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Acknowledgements

The authors wish to acknowledge Ansys/Lumerical, Siemens, and The MathWorks, Inc.

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  1. Department of Electronics and Communication Engineering, Madha Institute of Engineering and Technology, Chennai, India

    A. Mosses

  2. Department of Computer Science and Engineering, RMD Engineering College, Kavaraipettai, Chennai, India

    P. M. Joe Prathap

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Mosses, A., Joe Prathap, P.M. Analysis and codesign of electronic–photonic integrated circuit hardware accelerator for machine learning application. J Comput Electron 23, 94–107 (2024). https://doi.org/10.1007/s10825-023-02123-8

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