Abstract
An optical receiver employs an all-inverter-based front-end design that provides maximum transconductance for a given power supply and allows for ultra-low power consumption. The feedback transimpedance amplifier (TIA) input stage utilizes a multi-stage amplifier to achieve a dramatic increase in feedback resistance and lower input-referred noise. Cascading an inverter-based active inductor continuous-time linear equalizer provides frequency peaking to compensate the input stage TIA that is intentionally designed with a reduced bandwidth to achieve adequate sensitivity at low power. Fabricated in 28 nm CMOS, the 12.5 Gb/s optical receiver achieves \(-\)10.7 dBm OMA sensitivity at 0.11 pJ/bit energy efficiency and occupies only 720 \(\upmu \text {m}^{2}\) area.
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Data Availibility Statement
The authors declare that the data supporting the findings obtained during this research work is available within the paper.
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This research was funded by the DARPA PIPES program.
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PY designed the circuit and wrote the first draft of the manuscript. CH did test preparation and data collection. P-HC, HK, DA, AK, Y-HF, RL and RR contributed to the chip layout. SP gave advice during design procedure and commented on previous versions. All authors reviewed the final manuscript.
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Yan, P., Hong, C., Chang, PH. et al. A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer. Analog Integr Circ Sig Process 119, 283–296 (2024). https://doi.org/10.1007/s10470-024-02248-1
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DOI: https://doi.org/10.1007/s10470-024-02248-1