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A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches

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Abstract

With the development of semiconductor technology, the shrinking of feature size in integrated circuits has made them more sensitive to multiple-node-upsets (MNUs). Researchers have proposed various circuit-hardened methods, such as hardened latches, to address this issue. Currently, the reliability verification of latches relies on complex EDA tools, such as HSPICE, Cadence Virtuoso, and other tools for error injection. Therefore, this article proposes a high-performance quadruple-node-upset (QNU) tolerant latch design, called the HQNUT latch, based on 32 nm CMOS technology. Additionally, an algorithm-based latch verification process is proposed to enhance the efficiency and reliability of latch verification. This approach enables a fast and accurate assessment of the latch’s fault-tolerant capability. Due to clock gating technology and high-speed path technology, HQNUT’s power consumption and delay are reduced. Simulation results show that the proposed algorithm can certify the soft-error-tolerability of hardened Latches. Compared with existing QNU-tolerable hardened latches, the proposed latch reduced power consumption, area, delay, and power-delay product (PDP) by about 36.9%, 5.6%, 19.8%, and 46.4%, respectively.

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Data Availability

The datasets generated and analyzed during the current study are available from the corresponding author on reasonable request.

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Funding

This work was supported in part by the Special Fund for Research on National Major Research Instruments of China under grant 62027815.

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Authors and Affiliations

  1. School of Computer Science and Engineering, Anhui University of Science and Technology, Huainan, 232001, China

    Hui Xu, Xuewei Qin, Ruijun Ma, Chaoming Liu, Shuo Zhu & Jun Wang

  2. School of Microelectronics, Hefei University of Technology, Hefei, 230601, China

    Huaguo Liang

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  1. Hui Xu
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  2. Xuewei Qin
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  4. Chaoming Liu
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  5. Shuo Zhu
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  7. Huaguo Liang
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Correspondence to Huaguo Liang.

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Xu, H., Qin, X., Ma, R. et al. A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches. J Electron Test (2024). https://doi.org/10.1007/s10836-024-06105-x

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