Abstract
Intrinsically stretchable electronics with skin-like mechanical properties have been identified as a promising platform for emerging applications ranging from continuous physiological monitoring to real-time analysis of health conditions, to closed-loop delivery of autonomous medical treatment1,2,3,4,5,6,7. However, current technologies could only reach electrical performance at amorphous-silicon level (that is, charge-carrier mobility of about 1 cm2 V−1 s−1), low integration scale (for example, 54 transistors per circuit) and limited functionalities8,9,10,11. Here we report high-density, intrinsically stretchable transistors and integrated circuits with high driving ability, high operation speed and large-scale integration. They were enabled by a combination of innovations in materials, fabrication process design, device engineering and circuit design. Our intrinsically stretchable transistors exhibit an average field-effect mobility of more than 20 cm2 V−1 s−1 under 100% strain, a device density of 100,000 transistors per cm2, including interconnects and a high drive current of around 2 μA μm−1 at a supply voltage of 5 V. Notably, these achieved parameters are on par with state-of-the-art flexible transistors based on metal-oxide, carbon nanotube and polycrystalline silicon materials on plastic substrates12,13,14. Furthermore, we realize a large-scale integrated circuit with more than 1,000 transistors and a stage-switching frequency greater than 1 MHz, for the first time, to our knowledge, in intrinsically stretchable electronics. Moreover, we demonstrate a high-throughput braille recognition system that surpasses human skin sensing ability, enabled by an active-matrix tactile sensor array with a record-high density of 2,500 units per cm2, and a light-emitting diode display with a high refreshing speed of 60 Hz and excellent mechanical robustness. The above advancements in device performance have substantially enhanced the abilities of skin-like electronics.
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Acknowledgements
This work was partially supported by SAIT, Samsung Electronics, Army Research Office Bionic Electronics Program (grant no. W911NF-23-1-0282), CZ Biohub at San Francisco and Stanford Wearable Electronics Initiative (eWEAR). Part of this work was performed at the Stanford Nano Shared Facilities (SNSF), supported by the NSF award ECCS-2026822. We thank the Asahi Kasei Corporation for providing SEBS. We thank the Kraton Corporation for providing SBS. We thank Q. Liu, H. Yan, Y. Zheng, C. Zhu and Y. Jiang for their discussions.
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D.Z. and Z.B. conceived the project. D.Z. and Y.J. designed and developed the fabrication process. D.Z. and C.W. carried out the fabrication, measurement and demonstration. C.W., M.-g.K., Y.N., C.-C.S., W.W., Y.Y., N.M. and C.Z. provided inputs on the fabrication processes. D.Z., C.W., Y.N., W.W., Y.Y. and C.X. performed the electrical measurement. J.-C.L. measured the FT-IR spectrum. H.G. took the SEM images. Y.L. collected the UPS spectra. S.Z. performed the atomic force microscopy imaging. X.J., C.-C.S., Y.Z., Z.Y., D.L., J.-C.L. and Y.O. designed and synthesized the azide crosslinker and PFPD polymer. Y.-X.W. and Y.J. synthesized the polyrotaxane. T.Z.G., Y.N., C.-C.S. Y.Y. and D.Z. performed the CNT sorting. Y.Y., C.X., S.W. and S.L. helped with the demonstration. D.Z. carried out the modelling and simulation. D.Z., C.W., Y.J., J.B.-H.T. and Z.B. wrote the paper and incorporated the comments and edits from all authors.
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Stanford University is in the process of applying for a patent application 63/601,647 covering materials, device structure and fabrication process that lists Z.B., D.Z., C.W. and Y. J. as inventors.
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Extended data figures and tables
Extended Data Fig. 1 Patterning of M-CNT electrodes using metal-assisted lift off method.
a, Schematic diagram showing the process of making PMMA/metal stack structures. Cu was used for the metal layer because of its low cost and wide use in the industry manufacturing of commercial electronics. The thicknesses of PMMA, metal and photoresist are about 400 nm, 150 nm and 1.2 μm, respectively. b, Optical microscope image of the fabricated PMMA/Cu stack structures with different gap sizes. The channel length will be defined by the gap size and the minimal gap can be smaller than 1 μm. c, Optical microscope image of M-CNT electrodes with different channel lengths. d, Photo showing the lift-off procedure for patterning M-CNT electrodes. M-CNT on the metal is removed cleanly from the substrate together with the metal, when PMMA film underneath is dissolved in acetone.
Extended Data Fig. 2 Patterning of PEDOT:PSS/PR gate electrodes.
a, Schematic diagram showing the process of patterning of PEDOT:PSS gate electrodes. b-d, OM images of fabrication steps. e, OM image of PEDOT:PSS gate etching test structure. f, Current flow between two electrodes before and after PEDOT:PSS etching. g, OM image of structure for PEDOT:PSS conductivity measurement. h, Conductivity of PEDOT:PSS before and after HNO3 treatment.
Extended Data Fig. 3 Patterning of EGaIn electrodes.
a, Schematic diagram showing the process of patterning EGaIn. Printed EGaIn via blade coating using PDMS will form an alloy with the Cr/Au adhesion layer to make a stretchable conductor. b-c, Optical microscope images of photoresist on soft substrates using normal development process (b) and quasi-static development process (c). d-e, Optical microscope images of EGaIn lines w/o sonication (d) and w/ sonication (e). Ultrasonication is necessary to achieve small feature sizes. This method was adopted from a previous report (ref. S2) and modified for working on soft substrates. Because of the large modulus mismatch between the photoresist (GPa) and the soft substrate (MPa), the edges of photoresist can easily form fractures during the development and rinsing process. To solve this issue, we immersed the sample into the developer and DI water without any shaking, and then dried it by keeping the sample sitting vertical in air.
Extended Data Fig. 4 Photopatterning process of NBR dielectric.
a, Schematic diagram showing the process of patterning NBR dielectric. A reduction of peak intensity of the C-H stretching near 920 cm−1 from -C = C-H is an indicator of crosslinking of some of the vinyl groups. b, FT-IR spectrum of NBR-PETMP crosslinking reaction. The green shade marks the region for a zoom-in view on the right. c, OM image of the patterned NBR array. d, Thickness of NBR patterns versus exposure doses using different crosslinking approaches. Compared with the azide crosslinker (4 wt% vs NBR) that requires a 254 nm wavelength illumination and a high dose, PETMP (4 wt% vs NBR) based thiol crosslinker can induce NBR patterning using a 385 nm wavelength light source with a significantly reduced exposure dose. The error bars describe the standard error for three samples in each case.
Extended Data Fig. 5 Comparison of contact resistance w/ and w/o Pd interface layer.
a, Device structure of transistors w/o Pd. b, Device structure of transistors w/ Pd. c, Transfer curves of transistors with different channel length w/o Pd. Vds = −1.0 V. d, Transfer curves of transistors with different channel lengths w/ Pd. Vds = −1.0 V. e, Extraction of contact resistance of transistors w/o Pd. f, Extraction of contact resistance of transistors w/ Pd. Data from four transistors were averaged for each Lch.
Extended Data Fig. 6 Voltage transfer curves of small-size intrinsically stretchable Pseudo-CMOS inverters with forward and backward sweeps.
a, Optical microscope image of a Pseudo-D inverter. b, Circuit diagram of a Pseudo-D inverter. c, Optical microscope image of a Pseudo-E inverter. d, Circuit diagram of a Pseudo-E inverter. e, Representative voltage transfer curve of one out of three measured Pseudo-D inverters. f, Representative voltage transfer curve of one out of two measured Pseudo-E inverters. Both types of inverters show small hysteresis. The device area is about 0.03 mm2, only one-fifth of the published smallest intrinsic stretchable inverters10.
Extended Data Fig. 7 Size, orientation and location measurement using intrinsically stretchable active-matrix tactile sensor array.
(a) OM images (Top) and on-state current mapping (Bottom) of two rectangles with different sizes. (b) On-state current mapping of two triangles with different orientations. (c) On-state current mapping of three rectangles at different locations. To measure each pixel, the corresponding word line was set at −7 V, while other word lines were set at 1 V. Vds = −1 V.
Extended Data Fig. 8 Mechanical stability of intrinsically stretchable active-matrix tactile sensor array.
(a-b) Drain current of one pixel versus time during multiple pressing over 1000 times. The corresponding word line was set at −6 V, while other word lines were set at 1 V. Vds = −1 V. (c) Extracted average drain current versus pressing cycles. (d) On-state current mapping of a small rectangle shape (800×800 μm2) after over 1000cycles of pressing. To measure each pixel, the corresponding word line was set at −10 V, while other word lines were set at 1 V. Vds = −1 V.
Extended Data Fig. 9 Setup of LED display using intrinsically stretchable transistors.
(a) Schematic diagram of the display system. (b) Photography of the display system. Each LED is driven by a transistor, which is switched on and off by its gate voltage VCTL, i (i = 1, 2, …, 35). VCTL for the transistors is supplied by four 12-channel digital-to-analog converters (DACs). To monitor the total current under deformations, a transimpedance amplifier is used to convert the current into a voltage signal, which is further read out by an analog-to-digital converter (ADC). The system logic and timing are controlled by a microcontroller. MCU represents the microcontroller, and DACs represent the digital-to-analogy converters.
Extended Data Fig. 10 Drive a LED display using intrinsically stretchable transistors under strain.
(a) Measured on-state current and off-state current of a typical transistor during stretched, twisted, and relaxed. (b) Photographs of intrinsically stretchable transistor array under deformed/released and corresponding LED display images. The unchanged patterns/brightness of the LED display, while the transistors are being stretched, twisted, and relaxed, demonstrates the excellent mechanical robustness of the transistors.
Supplementary information
Supplementary Information
This file contains Supplementary Notes, Supplementary Figs. 1–65, Supplementary Tables 1–4, captions for Supplementary Videos 1–2 and Supplementary References.
Supplementary Video 1
Intrinsically stretchable transistors drive a display system showing different numbers, letters and symbols.
Supplementary Video 2
Intrinsically stretchable transistors drive a display system with a refreshing rate of 60 Hz.
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Zhong, D., Wu, C., Jiang, Y. et al. High-speed and large-scale intrinsically stretchable integrated circuits. Nature 627, 313–320 (2024). https://doi.org/10.1038/s41586-024-07096-7
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DOI: https://doi.org/10.1038/s41586-024-07096-7
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