Limiting Thickness of Pore Walls Formed in Processes of Anode Etching of Heavily Doped Semiconductors

Abstract

With a decrease in the thickness of the walls separating the space of pores in porous semiconductors, the potential energy of interaction between an electron and a donor (or a hole and an acceptor) can become greater than the kinetic energy of a free charge carrier. As a consequence, such interlayers lose their conductivity and transit into the dielectric state (Mott phase transition). With regard to the conditions of electrochemical pore formation, this means that as the pore channels approach each other during anodic etching to a distance at which the current flow through the wall that separates them stops, the potential of its surface ceases to be determined by the external electric bias and the electrochemical process, that leads to a further decrease in the thickness of such a wall, stops. Expressions are obtained for the limiting thickness of the walls of pores formed in degenerate semiconductors of n- and p-type conductivity. In contrast to the well-known model that relates the loss of conductivity by pore walls to the combination of space charge layers, the proposed model allows a consistent explanation for the experimental data for both n- and p-type silicon with doping levels above 10¹⁸ cm^–3.