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An FPGA-based front-end module emulator for the High Granularity Timing Detector

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Published 26 March 2024 © 2024 IOP Publishing Ltd and Sissa Medialab
, , Topical Workshop on Electronics for Particle Physics Citation Zhenwu Ge et al 2024 JINST 19 C03055 DOI 10.1088/1748-0221/19/03/C03055

1748-0221/19/03/C03055

Abstract

This paper introduces an FPGA-based front-end module emulator developed for the High Granularity Timing Detector (HGTD) within the ATLAS experiment at LHC. The emulator serves as a debugger for the HGTD readout system during the stage when the front-end module is not available. Using a Xilinx-Spartan 7 FPGA, the emulator mimics the behavior of the ASIC utilized in the front-end module. In addition, it shares the same dimensions and connectors as its successor, the real front-end module. This emulator has been effectively employed in the design and testing of the HGTD.

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