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Performance analysis of multi-folded pipelined successive cancellation decoder architecture for polar code

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Abstract

Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length \(N=512\) suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to \( 2^{10} \), compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications.

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Acknowledgements

The authors would like to thank SERB, DST for their financial support towards procuring EDA tools and hardware for this research under TARE scheme Grant number: TAR/2020/000001. The authors also thank Dr.Radhakrishna Ganti, Electrical Engineering IITM, for providing access to the 5G Lab and extending the necessary facilities.

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  1. Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamilnadu, 626005, India

    Dinesh Kumar D & Shantha Selvakumari R

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  1. Dinesh Kumar D
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Contributions

D.Dinesh Kumar: Conception, Methodology, Formal analysis, Software, Drafting, Investigation, Validation, editing the manuscript, R.Shantha Selvakumari: Investigation, Validation, Reviewing the manuscript critically for important intellectual content, Supervision.

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Correspondence to Dinesh Kumar D.

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D, D.K., R, S.S. Performance analysis of multi-folded pipelined successive cancellation decoder architecture for polar code. Sādhanā 49, 144 (2024). https://doi.org/10.1007/s12046-024-02503-1

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