Skip to main content
SpringerLink
Log in

Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Approximate Computing (AxC) aims at optimizing the hardware resources in terms of area and power consumption at the cost of a reasonable degradation in computation accuracy. Several design exploration approaches and metrics have been proposed so far to identify the approximation targets, but only a few of them exploit information derived from assertion-based verification (ABV). In this paper we propose an ABV methodology to guide the AxC design exploration of RTL descriptions; we consider two main approximation techniques: bit-width and statement reduction. Assertions are automatically mined from the simulation traces of the original design to capture the golden behaviours. Then, we consider the syntactic and semantic aspects of the assertions to rank the approximation targets. The proposed methodology generates a list of statements sorted by their increasing impact on altering the functional correctness of the original design, when selected to be approximated. Through experiments on a case study, we show that the proposed approach represents a promising solution toward the automation of AxC design exploration at RTL.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Algorithm 1
Fig. 5
Algorithm 2
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

Data availability

The implementation of methodology presented in the paper is fully accessible from https://github.com/SamueleGerminiani/harm/tree/main/src/dea. The repository contains all the used data.

Notes

  1. The testbench affects the quality of the mined assertions, as it happens in any other simulation-based verification approach. It is reasonably to assume that in a simulation-based verification flow a high-quality test set is available at the time assertion mining is executed.

References

  1. Barbareschi M, Barone S, Bosio A, Han J, Traiola M (2022) A genetic-algorithm-based approach to the design of DCT hardware accelerators. ACM J Emerg Technol Comput Syst 18(3):1–25

    Article  Google Scholar 

  2. Barone S, Traiola M, Barbareschi M, Bosio A (2021) Multi-objective application-driven approximate design method. IEEE Access 9:86975–86993

    Article  Google Scholar 

  3. Bosio A, Bragaglio M, Germiniani S, Mori S, Pravadelli G, Traiola M (2022) Assertion-aware approximate computing design exploration on behavioral models. In: 2022 IEEE 23rd Latin American Test Symposium (LATS), pp 1–6

  4. Bosio A, Menard D, Sentieys O (eds) (2022) Approximate computing techniques, 1st edn. Cham, Switzerland, Springer Nature

    Google Scholar 

  5. Chippa VK, Chakradhar ST, Roy K, Raghunathan A (2013) Analysis and characterization of inherent application resilience for approximate computing. In: Proceedings of ACM/IEE DAC

  6. Foster H, Lacey D, Krolnik A (2003) Assertion-based design, 2nd edn. Kluwer Academic Publishers, USA

    Book  Google Scholar 

  7. Germiniani S, Pravadelli G (2022) Harm: a hint-based assertion miner. IEEE Trans Comput Aided Des Integr Circ Syst 41(11):4277–4288

    Article  Google Scholar 

  8. Han J, Orshansky M (2013) Approximate computing: an emerging paradigm for energy-efficient design. In: Proceedings of IEEE ETS

  9. https://github.com/SamueleGerminiani/harm. Accessed 22 Jan 2024

  10. Huang P, Wang C, Liu W, Qiao F, Lombardi F (2021) A hardware/software co-design methodology for adaptive approximate computing in clustering and ANN learning. IEEE Open J Comput Soc 2:38–52

    Article  Google Scholar 

  11. Isenberg FPT, Jakobs MC, Wehrheim H (2018) Validity of software verification results on approximate hardware. In: IEEE Embedded Systems Letters

  12. Jiang H, Santiago FJH, Mo H, Liu L, Han J (2020) Approximate arithmetic circuits: a survey, characterization, and recent applications. Proc IEEE 108(12):2108–2135

    Article  Google Scholar 

  13. Lee S, John LK, Gerstlauer A (2017) High-level synthesis of approximate hardware under joint precision and voltage scaling. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp 187–192

  14. Liu W, Cao T, Yin P, Zhu Y, Wang C, Swartzlander EE, Lombardi F (2018) Design and analysis of approximate redundant binary multipliers. IEEE Trans Comput 68(6):804–819

    Article  MathSciNet  Google Scholar 

  15. Liu W, Lombardi F, Shulte M (2020) A retrospective and prospective view of approximate computing. Proc IEEE 108(3):394–399

    Article  Google Scholar 

  16. Lloyd S (1982) Least squares quantization in PCM. IEEE Trans Inf Theory 28(2):129–137

    Article  MathSciNet  Google Scholar 

  17. Ma D, Thapa R, Wang X, Hao C, Jiao X (2021) Workload-aware approximate computing configuration. In: Design, Automation Test in Europe Conference Exhibition (DATE) (in press), pp 258–261

  18. Mitra S, Das M, Banerjee A, Datta K, Ho T-Y (2016) A verification guided approach for selective program transformations for approximate computing. In: Proceedings of IEEE ATS

  19. Mittal S (2016) A survey of techniques for approximate computing. ACM Comput Surv 48(4):62:1-62:33

    Article  Google Scholar 

  20. Mrazek V, Sekanina L, Vasicek Z (2020) Libraries of approximate circuits: Automated design and application in CNN accelerators. IEEE J Emerg Select Topics Circ Syst 10(4):406–418

    Article  Google Scholar 

  21. Nepal K, Li Y, Bahar R, Reda S (2014) Abacus: a technique for automated behavioral synthesis of approximate computing circuits. In: Proceedings of ACM/IEEE DATE

  22. Sampson A, Baixo A, Ransford B, Moreau T, Yip J, Ceze L, Oskin M (2015) Accept: a programmer-guided compiler framework for practical approximate computing. University of Washington Technical Report UW-CSE-15-01 (vol. 1, no. 2)

  23. Sidiroglou-Douskos S, Misailovic S, Hoffmann H, Rinard M (2011) Managing performance vs. accuracy trade-offs with loop perforation. In: Proceedings of ACM ESEC/FSE

  24. Venkataramani S, Chakradhar ST, Roy K, Raghunathan A (2015) Approximate computing and the quest for computing efficiency. In: Proceedings of ACM/IEE DAC

  25. Wang Z, Bovik AC, Sheikh HR, Simoncelli EP (2004) Image quality assessment: From error visibility to structural similarity. IEEE Trans Image Process 13(4):600–612

    Article  Google Scholar 

  26. Ye XFM, Wei S (2019) Runtime hardware security verification using approximate computing: a case study on video motion detection. In: Proceedings of IEEE AsianHOST

  27. Yoshisue YMK, Ishihara T (2021) Dynamic verification of approximate computing circuits using coverage-based grey-box fuzzing. In Proceedings of IEEE IOLTS

  28. Zervakis G, Amrouch H, Henkel J (2020) Design automation of approximate circuits with runtime reconfigurable accuracy. IEEE Access 8:53522–53538

    Article  Google Scholar 

  29. (2010) Standard for property specification language (PSL). IEEE Std 1850-2010 (Revision of IEEE Std 1850-2005), 1–182. https://doi.org/10.1109/IEEESTD.2010.5446004

Download references

Funding

This work has been partially supported by the INdAM GNCS, and it was carried out within the PNRR research activities of the consortium iNEST (Interconnected North-Est Innovation Ecosystem) funded by the European Union Next-GenerationEU (PNRR - Missione 4 Componente 2, Investimento 1.5 - D.D. 1058 23/06/2022, ECS-00000043).

Author information

Authors and Affiliations

  1. Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, Lyon, France

    Alberto Bosio

  2. Department of Engineering for Innovation Medicine, University of Verona, Verona, Italy

    Samuele Germiniani & Graziano Pravadelli

  3. University of Rennes, Inria, CNRS, IRISA, UMR6074, Rennes, France

    Marcello Traiola

Authors
  1. Alberto Bosio
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Samuele Germiniani
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Graziano Pravadelli
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Marcello Traiola
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Alberto Bosio.

Ethics declarations

Conflict of interest

The authors declare no conflict of interests.

Additional information

Responsible Editor: L.M.B Poehls

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bosio, A., Germiniani, S., Pravadelli, G. et al. Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs. J Electron Test (2024). https://doi.org/10.1007/s10836-024-06115-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s10836-024-06115-9

Keywords

Search

Navigation