The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson (multiplicative) method and it supports all IEEE rounding modes with a latency of 15 cycles. The iterative NR computations are performed by using FP multiplier and FP adder. The key module of FP multiplier for calculating mantissa part is UT multiplier. It’s an ancient Vedic multiplication technique used from few centuries back for doing fast multiplications. We implemented two UT multipliers: one using carry look-ahead adders and another one using carry save adders. The results show that, the proposed architectures have 12% better precision with 24% high throughput than existing algorithms, at the cost of high on-chip power. The inputs to the divider are represented in IEEE-754 standard. The design uses Xilinx Vivado software and it is implemented on Virtex7 FPGA.

中文翻译：

---

使用Urdhva–Tiryakbhyam乘法器为SoC应用实现高精度/低延迟FP分频器

工业和科学数据密集型应用的不断增长的需求是具有减少计算时间的高精度算术。在本文中，我们设计了一种高精度的全流水线32位浮点（FP）分频器，它使用牛顿-拉夫森（NR）算法和Urdhva-Tiryakbhyam（UT）乘法器实现了片上系统应用。分频器设计基于牛顿-拉夫森（乘法）方法，并支持15个周期的延迟的所有IEEE舍入模式。迭代NR计算是使用FP乘法器和FP加法器执行的。用于计算尾数部分的FP乘法器的关键模块是UT乘法器。这是一种古老的吠陀乘法技术，距今已有几个世纪，用于进行快速乘法。我们实现了两个UT乘法器：一个使用进位预存加法器，另一个使用进位保存加法器。结果表明，与现有算法相比，所提出的架构具有12％的精度和24％的高吞吐量，但代价是片上功耗较高。分频器的输入以IEEE-754标准表示。该设计使用Xilinx Vivado软件，并在Virtex7 FPGA上实现。