The number of battery-powered devices is rapidly increasing due to the widespread use of IoT-enabled nodes in various fields. Energy harvesters, which help to power embedded devices, are a feasible alternative to replacing battery-powered devices. In a capacitor, the energy harvester stores enough energy to power up the embedded device and compute the task. This type of computation is referred to as intermittent computing. Energy harvesters are unable to supply continuous power to embedded devices. All registers and cache in conventional processors are volatile. We require a Non-Volatile Memory (NVM)-based Non-Volatile Processor (NVP) that can store registers and cache contents during a power failure. NVM-based caches reduce system performance and consume more energy than SRAM-based caches. This paper proposes Efficient Placement and Migration policies for hybrid cache architecture that uses SRAM and STT-RAM at the first level cache. The proposed architecture includes cache block placement and migration policies to reduce the number of writes to STT-RAM. During a power failure, the backup strategy identifies and migrates the critical blocks from SRAM to STT-RAM. When compared to the baseline architecture, the proposed architecture reduces STT-RAM writes from 63.35% to 35.93%, resulting in a 32.85% performance gain and a 23.42% reduction in energy consumption. Our backup strategy reduces backup time by 34.46% when compared to the baseline.

由于支持物联网的节点在各个领域的广泛使用，电池供电设备的数量正在迅速增加。能量收集器有助于为嵌入式设备供电，是替代电池供电设备的可行替代方案。在电容器中，能量收集器存储足够的能量来为嵌入式设备供电并计算任务。这种类型的计算称为间歇计算。能量采集器无法为嵌入式设备持续供电。传统处理器中的所有寄存器和高速缓存都是易失性的。我们需要一个基于非易失性存储器 (NVM) 的非易失性处理器 (NVP)，它可以在电源故障期间存储寄存器和缓存内容。基于 NVM 的缓存会降低系统性能并比基于 SRAM 的缓存消耗更多的能量。本文提出了在一级缓存中使用 SRAM 和 STT-RAM 的混合缓存架构的高效放置和迁移策略。提议的架构包括缓存块放置和迁移策略，以减少写入 STT-RAM 的次数。在电源故障期间，备份策略识别关键块并将其从 SRAM 迁移到 STT-RAM。与基线架构相比，所提出的架构将 STT-RAM 写入从 63.35% 减少到 35.93%，从而带来 32.85% 的性能提升和 23.42% 的能耗降低。与基线相比，我们的备份策略将备份时间减少了 34.46%。提议的架构包括缓存块放置和迁移策略，以减少写入 STT-RAM 的次数。在电源故障期间，备份策略识别关键块并将其从 SRAM 迁移到 STT-RAM。与基线架构相比，所提出的架构将 STT-RAM 写入从 63.35% 减少到 35.93%，从而带来 32.85% 的性能提升和 23.42% 的能耗降低。与基线相比，我们的备份策略将备份时间减少了 34.46%。提议的架构包括缓存块放置和迁移策略，以减少写入 STT-RAM 的次数。在电源故障期间，备份策略识别关键块并将其从 SRAM 迁移到 STT-RAM。与基线架构相比，所提出的架构将 STT-RAM 写入从 63.35% 减少到 35.93%，从而带来 32.85% 的性能提升和 23.42% 的能耗降低。与基线相比，我们的备份策略将备份时间减少了 34.46%。