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Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors
Quantum Science and Technology ( IF 6.7 ) Pub Date : 2024-02-02 , DOI: 10.1088/2058-9565/ad199c Nandini Muthusubramanian , Matvey Finkel , Pim Duivestein , Christos Zachariadis , Sean L M van der Meer , Hendrik M Veen , Marc W Beekman , Thijs Stavenga , Alessandro Bruno , Leonardo DiCarlo
Quantum Science and Technology ( IF 6.7 ) Pub Date : 2024-02-02 , DOI: 10.1088/2058-9565/ad199c Nandini Muthusubramanian , Matvey Finkel , Pim Duivestein , Christos Zachariadis , Sean L M van der Meer , Hendrik M Veen , Marc W Beekman , Thijs Stavenga , Alessandro Bruno , Leonardo DiCarlo
We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to
∼ 100 M H z in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.
更新日期：2024-02-02
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