This article proposes a two-stage time-to-digital converter with a novel method for enhancing resolution and using digital error correction called time-to-digital converter with enhanced resolution (TDC-ER). The proposed TDC is composed of two Vernier TDCs and operating in two stages. The first stage uses a normal Vernier TDC with a 512 ps range, and the second stage employs a 2D Vernier TDC with a new delay element. The second stage can achieve a fine resolution of 2 ps. This study presents a novel idea for boosting the resolution by analyzing D flip-flop (DFF) outputs in the metastability state. In the end, it is shown that this method can achieve a 1 ps resolution. The TDC-ER offers the benefits of new digital error correction, reducing the connection error between two stages and increasing linearity. A new calibration idea is presented in this work. This circuit is designed and simulated using a 65-nm standard CMOS technology, and the simulation result demonstrates a 1.56 ps effective resolution and a 9-bit range. It operates at 250 MS/s while consuming about 0.5 mW power from a 1.2-V supply.

本文提出了一种两级时间数字转换器，采用一种增强分辨率和使用数字纠错的新颖方法，称为增强分辨率时间数字转换器 (TDC-ER)。拟议的 TDC 由两个 Vernier TDC 组成，并分两个阶段运行。第一级使用具有 512 ps 范围的普通 Vernier TDC，第二级采用带有新延迟元件的 2D Vernier TDC。第二级可以实现2 ps的精细分辨率。这项研究提出了一种通过分析亚稳态下 D 触发器 (DFF) 输出来提高分辨率的新颖想法。最后表明该方法可以达到1 ps的分辨率。TDC-ER 具有新的数字纠错功能，可减少两级之间的连接误差并提高线性度。这项工作提出了一种新的校准思想。该电路采用65 nm标准CMOS工艺进行设计和仿真，仿真结果显示有效分辨率为1.56 ps，范围为9位。它的运行速度为 250 MS/s，同时使用 1.2V 电源消耗约 0.5 mW 的功率。