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High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2024-04-10 , DOI: 10.1109/ted.2024.3384133 Yao-Hung Huang, Yu-Cheng Hsieh, Yu-Cheng Lin, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King, Chrong Jung Lin
中文翻译：
采用 16 nm FinFET CMOS 逻辑工艺的高密度嵌入式 3D 可堆叠通过 RRAM
更新日期：2024-04-10
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2024-04-10 , DOI: 10.1109/ted.2024.3384133 Yao-Hung Huang, Yu-Cheng Hsieh, Yu-Cheng Lin, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King, Chrong Jung Lin
中文翻译：
采用 16 nm FinFET CMOS 逻辑工艺的高密度嵌入式 3D 可堆叠通过 RRAM
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