Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length \(N=512\) suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to \( 2^{10} \), compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications.

Polar 码是流行的纠错码，在第五代新无线电 (5G NR) 标准中用于控制信道后，引起了人们的关注。 Polar 码通常需要高效的硬件架构，同时具有最小的编码和解码复杂性。这项工作提出了一种多重流水线架构，并分析了延迟、硬件利用率和吞吐量方面的性能。设计的架构具有两个并行互连的折叠架构，可同时输出 4 位。折叠变换用于减少每个阶段闲置处理元素（PE）的数量，从而有效利用PE。 PE中有效利用预计算来减少关键路径延迟，从而提高最大工作频率。采用基于循环的移位寄存器（LSR）来减少使用的寄存器数量。延迟和利用率的分析模型是从所提出的架构的调度中得出的。对于适合 5G NR 中物理下行链路控制信道 (PDCCH) 的码长\(N=512\)，所提出的设计显示出比传统半并行设计高 63-71% 的硬件利用率。该架构还在 Virtex-6、ZYNQ-Ultrascale+ MPSoC 器件中实现，与现有解码器相比，最大支持 5G NR 代码长度，即高达\( 2^{10} \) 。所提出的设计还具有较少的查找表 (LUT) 消耗和零随机存取存储器 (RAM) 使用以及一些附加寄存器的优点，使其适合资源受限的应用。