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On the improved RF performance of step field plate LDMOS transistor Microelectron. J. (IF 2.2) Pub Date : 2024-04-16 Rutu Patel, Nihar R. Mohapatra
This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage () and low specific on-resistance (). Significant improvement in frequency behavior is observed
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Unveiling the influence of temperature and interface traps on the performance of source-all-around vertical TFET Microelectron. J. (IF 2.2) Pub Date : 2024-04-16 Potharaju Ramesh, Bijit Choudhuri
This study investigates the electrical performance of a line-tunneling based source-all-around vertical Tunnel Field-Effect Transistor (SAA-VTFET) under diverse temperature and trap charge conditions. The proposed device achieves remarkable performance improvements across DC and AC parameters by employing strategically engineered III-V semiconductors and a wide source-channel tunneling heterojunction
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Improvement of C-shaped pocket TFET with sandwiched drain for ambipolar performance and analog/RF performance Microelectron. J. (IF 2.2) Pub Date : 2024-04-15 Wanyang Xiao, Liang Wang, Yu Peng, Yafei Ding, Yingjie Ma, Fang Yang, Weijing Liu, Zimiao Zhao, Jie Xu, Min Tang, Wei Bai, Xiaodong Tang
A novel structure of tunneling field effect transistor device (CSP-SD-TFET) is proposed, which adds a sandwiched drain to the C-shaped pocket TFET (CSP-TFET). This structure can increase the resistance of the drain, share the lateral electric field at the tunneling junction between the channel and the drain, reduce the lateral electric field at the tunneling junction, and suppress the generation of
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A compact Non-Quasi-Static small-signal model for GaN HEMT Microelectron. J. (IF 2.2) Pub Date : 2024-04-12 Behnam Jafari Touchaei, Majid Shalchian
In this work, we introduce a compact Non-Quasi-Static (NQS) model for the long-channel Gallium nitride high-mobility field effect transistor based on charge-based EPFL (École Polytechnique fédérale de Lausanne) HEMT model implemented in Verilog-AMS modeling language. The proposed model has been validated for the low-frequency (quasi-static) operating region as well as high frequencies up to sub-terahertz
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Recent advances on reliability of FPGAs in a radiation environment Microelectron. J. (IF 2.2) Pub Date : 2024-04-12 Zhe Liu, Zukun Lu, Long Huang, Zhiwei Yao, Zhaojun Lu, Jiliang Zhang
In recent years, SRAM-based Field-Programmable Gate Arrays (FPGAs) have seen a surge in deployment within aerospace applications. Despite their widespread use, these FPGAs, particularly their embedded Static Random Access Memory (SRAM) and user logic, exhibit a notable susceptibility to Single Event Upsets (SEU), a phenomenon leading to erroneous connections or routing discrepancies. This paper presents
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A 180 fps WVGA CIS with 3.2e− TRN and dual-readout modes Microelectron. J. (IF 2.2) Pub Date : 2024-04-11 Xiaoxuan Liu, Tianjiao Cao, Haisong Li, Xin Yuan, Wancheng Xu, Ting Li
In order to broaden the application scenarios and reduce the noise performance for global shutter CMOS image sensors (CISs), this paper proposes a low-noise and dual-readout-modes global shutter WVGA CIS. By implementing buried channel nMOS and pMOS without body effect as the source followers of 8-transistors active pixel (8TAP), the noise performance of the sensor is optimized. Moreover, based on
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Improving the computational efficiency and flexibility of FPGA-based CNN accelerator through loop optimization Microelectron. J. (IF 2.2) Pub Date : 2024-04-10 Yuhao Liu, Yanhua Ma, Bowei Zhang, Lu Liu, Jie Wang, Shibo Tang
The convolution operation consists of three-dimensional multiply-accumulate (MAC) operations within four loops, leading to a large design space to be optimized. However, prior research did not thoroughly investigate the loop optimization operations, which led to the development of accelerators that employed inefficient parallel computing architectures and hence consumed unnecessary resources. This
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Temperature rise detection in GaN high-electron-mobility transistors via gate-drain Schottky junction forward-conduction voltages Microelectron. J. (IF 2.2) Pub Date : 2024-04-09 Xiujuan Huang, Chunsheng Guo, Qian Wen, Shiwei Feng, Yamin Zhang
An electrical measurement method for the junction temperature and thermal resistance of GaN high-electron-mobility transistors (HEMTs) is discussed. It is based on the forward voltage drop across the gate-drain Schottky diode. During measurement of this temperature-sensitive parameter, the source is left floating while the drain is grounded. Previous studies have shown that the hot spot in GaN HEMTs
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A 6-/12-dB back-off reconfigurable Doherty-like load modulated balanced amplifier with compact area and wide bandwidth Microelectron. J. (IF 2.2) Pub Date : 2024-04-09 Xianfeng Que, Yanjie Wang, Shangyao Huang
This article presents a Doherty-like Reconfigurable Load Modulated Power Amplifier (R-LMBA) topology, which enables a broadband 6-/12-dB power back-off (PBO) reconfiguration by rearranging the bias voltages of the sub-amplifiers with compact area. The proposed R-LMBA guarantees proper phase differences among the three sub-PAs across the entire operating frequency band without the need for a bulky phase
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Novel high-voltage GaN CAVET with high threshold voltage and low reverse conduction loss Microelectron. J. (IF 2.2) Pub Date : 2024-04-09 Chengtao Luo, Cheng Yang, Zhijia Zhao, Xintong Xie, YuXi Wei, Jie Wei, Jingyu Shen, Jinpeng Qiu, Xiaorong Luo
A novel GaN current-aperture vertical electron transistor (CAVET) with an energy band pinning (EBP) structure (EBP-CAVET) is proposed and investigated by simulations. The EBP-CAVET is featured with hybrid contacts on the p-GaN layer, locally having Ohmic contact combined with Schottky gate metals in the longitudinal direction. The Ohmic contact is shorted to the source electrode and the Schottky gate
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Suppressed current collapse and improved threshold voltage stability of AlGaN/GaN HEMT via O2 plasma treatment Microelectron. J. (IF 2.2) Pub Date : 2024-04-09 Yitai Zhu, Yu Zhang, Haolan Qu, Han Gao, Haitao Du, Haowen Guo, Xinbo Zou
A comprehensive study about the effects of O plasma treatment on the dynamic performance of AlGaN/GaN high electron mobility transistors (HEMTs) is presented. The drain current transient spectroscopy indicated a much decelerated and mitigated current degradation process for the HEMT with O plasma treatment. Upon negative gate bias stressing, current collapse of 10.7 % and minor threshold voltage shift
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Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design Microelectron. J. (IF 2.2) Pub Date : 2024-04-09 Priyanka, Sangeeta Singh, Meena Panchore
This article investigates the performance of a vertically extended drain double gate Si Ge source tunnel field effect transistor (VD-DG-Si Ge S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si Ge S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si Ge S-TFET requires a low spiking threshold voltage
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A symmetrical fully-integrated CMOS doherty power amplifier Microelectron. J. (IF 2.2) Pub Date : 2024-04-08 Samira Ebazadeh, Masoud Meghdadi, Ali Medi
This paper presents a new method to enhance the efficiency of a symmetrical doherty power amplifier (DPA) by fully utilizing the current driving capability of a class-C biased peaking amplifier. In this method, with utilization of the passive voltage gain concept, the input matching networks are designed in a way that the peaking path experiences a higher voltage gain than the carrier path, at high
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Device parameter prediction for GAA junctionless nanowire FET using ANN approach Microelectron. J. (IF 2.2) Pub Date : 2024-04-07 Abhishek Raj, Shashi Kant Sharma
The primary objective of this study is to investigate the potential of artificial neural network (ANN) for predicting the short-channel effect parameters and current-voltage curve in gate-all-around junctionless nanowire FET (GAA-JL-NWFET). The evaluation of the effectiveness of an ANN is typically done by analyzing metrics like root mean square error (RMSE) and coefficient of determination (R-score)
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VLSI design for adjustable compression rate in lossless/lossy compression of EEG signal Microelectron. J. (IF 2.2) Pub Date : 2024-04-06 Haotian Yu, Yaguang Yang, Daibo Zhang, Qiliang Zhang, Zhiqiang Li
In the realm of remote health monitoring, the compression of electroencephalography (EEG) signals at the edge holds significant importance. This paper presents a VLSI structure capable of adjustable compression rates to achieve both lossless and lossy compression of EEG data, catering to environments requiring flexible adjustment of compression types and rates. The architecture integrates two-dimensional
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Analytical modeling of drain current for DG-Graphene Nanoribbon Vertical Tunnel FET Microelectron. J. (IF 2.2) Pub Date : 2024-04-06 Zohmingliana, Bijit Choudhuri, Brinda Bhowmick
The semi-classical current transport model is used in this study to examine the drain current model for Double-Gate (DG) Dual-Material-Gate (DMG) Graphene-Nanoribbon (GNR) Vertical TFETs. It takes into account the contact potential (V, V), the impact of the oxide thickness (t), and the carrier mobility (). The device’s channel length is 50 nm, and the energy bandgap is 0.26 eV when the GNR ribbon width
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Novel fast-switching P-poly trench collector reverse conducting IGBT with different N-buffer position Microelectron. J. (IF 2.2) Pub Date : 2024-04-04 Yuying Wang, Zhengyuan Zhang, Peng Jian, Pengfei Liao, Aohang Zhang, Kunfeng Zhu, Wensuo Chen
A novel fast-switching P-poly trench collector reverse-conducting insulated gate bipolar transistor (RC-IGBT) with different N-buffer position (DBP) is proposed and investigated. Firstly, the N-buffer on P-poly Trench-Collector (TC) not on P+ and N+ collector will unaffected realize snapback-free with and without interface charge exist in the forward conduction. Secondly, N-buffer on TC can keep the
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A novel nanosheet reconfigurable field effect transistor with dual-doped source/drain Microelectron. J. (IF 2.2) Pub Date : 2024-04-02 Bin Lu, Xiaotao Liu, Zhu Li, Jiayu Di, Dawei Wang, Yulei Chen, Linpeng Dong, Yuanhao Miao
—In this paper, a reconfigurable field-effect transistor (RFET) with dual-doped nanosheet architecture and triple independent gates is proposed and studied with the numerical simulations. The proposed RFET can behave as either an n/p-type MOSFET or an n/p-type tunneling-FET (TFET) according to different program biases. A comprehensive study is carried out on the device mechanism and the influence of
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Reduction of off-state drain current in AlN/[formula omitted] HEMT by trap state engineering Microelectron. J. (IF 2.2) Pub Date : 2024-04-01 Aishwarya Tomar, Satyendra Kumar Mourya, Rahul Kumar
In this work, we report various strategies to reduce the off-state drain leakage current () in AlN/ high electron mobility transistor (HEMT) by 2D device simulation. We have investigated the effect of access region, channel doping concentration, barrier layer thickness, and trap state engineering on . The formation of a parallel channel deep into the substrate has been found to be responsible for large
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Cross-coupled 4T2R multi-logic in-memory computing circuit design Microelectron. J. (IF 2.2) Pub Date : 2024-04-01 Zhiting Lin, Changxin Yue, Ke Li, Qiushi Feng, Siyan Li, Yue Zhao, Yuanyang Wang, Jiaqi Chen, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Chenghu Dai, Licai Hao, Xiulong Wu
Resistive random access memory (RRAM) is viewed as the next-generation memory model, surpassing the constraints of traditional random access memory. Given its non-volatile nature, which lessens static power consumption, RRAM boasts significant computing-in-memory (CIM) potential. We herein present a four-transistor/two-resistor cross-coupling structure based on RRAM. In this structure, two RRAMs are
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A novel 4H–SiC IGBT with double gate PMOS for improving the switch controllability and FBSOA Microelectron. J. (IF 2.2) Pub Date : 2024-03-31 Lijuan Wu, Deqiang Yang, Guanglin Yang, Dongsheng Zhao, Jie Yuan, Zigui Tu, Mengjiao Liu
In this work, a 4H–SiC insulated-gate bipolar transistor (IGBT) with double gate PMOS (DGPMOS) is proposed. In the on-state, DGPMOS IGBT can form a hole barrier, thus reducing the on-state voltage (ON). During the turn-on and turn-off transients, DGPMOS IGBT can form the extra hole extraction paths. This helps to reduce the turn-off loss (off) and the gate displacement current (G_dis). The simulation
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A TDC-assisted SAR ADC with high-speed sampling switches and fine-tuned delay cells Microelectron. J. (IF 2.2) Pub Date : 2024-03-31 Chengcheng Zhang, Ang Hu, Dongsheng Liu, Shuo Ma, Hao Li, Zirui Jin
—This paper presents a 10-bit two-step successive approximation register (SAR) analog-to-digital converter (ADC) based on voltage and time quantization. To reduce S/H circuit leakage current and increase sampling rate at low supply voltage, a new high-speed low-leakage double-bootstrapped sample-and-hold switch (HSLL-DB-SH) is proposed. The LSB gain error between the coarse ADC and fine time-to-digital
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Modeling and signal integrity analysis of silicon interposer channels based on MTL and KBNN Microelectron. J. (IF 2.2) Pub Date : 2024-03-31 Wen-Bin Gao, Xuan Lin, Guo-Sheng Li, Hong-Shun Yin, Fei-Long Lv, Peng Zhang, Da-Wei Wang, Wen-Sheng Qian, Hao Zhang, Wen-Sheng Zhao
In this paper, the equivalent circuit model of interconnect channels in silicon interposer is developed for three-dimensional integrated circuit (3-D IC) based on the theory of multi-conductor transmission line (MTL). The deep neural network (DNN) is employed to learn the nonlinear mapping relationship between the geometric parameters and the distributed parameters, and it is demonstrated that the
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A leakage-suppressed capacitive-feedback amplifier scheme for event-based vision sensors in scaled-down technology Microelectron. J. (IF 2.2) Pub Date : 2024-03-28 Zhiyuan Gao, Siwei He, Xiaopei Shi, Jiangtao Xu
This paper presents a leakage-suppressed capacitive-feedback amplifier (LSCFA) scheme for event-based vision sensors (EVS) to reduce the background event rate. Compared with the traditional capacitive-feedback amplifier (CFA) that employs power voltage as the reset voltage of the switch, the proposed LSCFA utilizes the output voltage in the reset state as the reset voltage of the switch. The proposed
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A single-chip PFM-controlled LED driver with 0.5% illuminance variation Microelectron. J. (IF 2.2) Pub Date : 2024-03-26 Chua-Chin Wang, L S S Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo
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Design and investigation of double-RESURF SOI-LIGBT with carrier-storage layer in P-top Microelectron. J. (IF 2.2) Pub Date : 2024-03-23 Zhigang Shen, Pengfei Liao, Qisheng Yu, Jiaweiwen Huang, Aohang Zhang, Wensuo Chen
A novel double-RESURF SOI-LIGBT with carrier-storage layer in P-top (CSLP-LIGBT) is proposed and studied by simulation. The carrier storage layer avoids direct connection between the P-top region and the P+ region, enhancing the carrier storage effect in the drift region during the on-state. CSLP-LIGBT provides a fast hole-extraction channel during the turn-off transient, shortening the turn-off time
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Splicable random windowing row selection circuit for large array CMOS image sensor Microelectron. J. (IF 2.2) Pub Date : 2024-03-21 Changju Liu, Zhijun Wu, Kaiming Nie, Yiqiang Li, Jiangtao Xu, Xiuyu Wang, Ying Wang, Rui Gong, Jiaqi Lu
This paper presents a splicable random window row selection circuit applied to large array CMOS image sensors (CIS) for exposure and readout of certain pixel rows in large array CIS. The row selection circuit consists of coarse decoding and fine decoding circuits, utilizing two-stage address selection operations for precise row selection. The coarse decoding address is used to enable the splicing module
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Configurable in-memory computing architecture based on dual-port SRAM Microelectron. J. (IF 2.2) Pub Date : 2024-03-19 Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin
In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit
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Intrinsic point defects investigation in InAlAs with extrapolated defect transition level Microelectron. J. (IF 2.2) Pub Date : 2024-03-19 Yuxin Fang, Jialin Zhang, Yongbo Su, Zhi Jin, Yinghui Zhong
The intrinsic point defects in InAlAs have been studied by first-principles calculations, with a simplified approach to rescale the charge transition levels from the semilocal to the hybrid functional level. Both antisite defects and vacancy defects exhibit a high sensitivity to growth conditions. For Al-poor, In-poor and As-poor growth conditions, As, As and V demonstrate the lowest defect formation
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Evolutionary algorithm for minimizing the temperature influence of low power RF Energy Harvesting circuits Microelectron. J. (IF 2.2) Pub Date : 2024-03-18 Renan Trevisoli, Lícia S.C. Lima, Humberto P. da Paz, Rodrigo T. Doria, Ivan R.S. Casella, Carlos E. Capovilla
The aim of this work is to analyze and optimize the design of low-power Radio Frequency (RF) Energy Harvesting rectifiers by using an Evolutionary Algorithm. Although, generally neglected in the literature, the RF rectifier operation strongly depends on the operation temperature. When it varies, the input impedance can change significantly, affecting the circuit matching and its power conversion efficiency
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Frontiers and challenges in silicon-based single-photon avalanche diodes and key readout circuits Microelectron. J. (IF 2.2) Pub Date : 2024-03-16 Yang Liu, Linlin Wang, Liang Gao, Ruiqi Fan, Xing Su, Linjie Shen, Shiliang Pu, Liming Wang, Zhangming Zhu
Single-photon detectors enable the detection of extremely weak light with remarkable temporal precision. This capability provides crucial technological support for precise distance measurements and high-resolution imaging under low-light conditions. Silicon and silicon-based germanium single-photon detectors can operate in a wide spectrum from the visible to the near-infrared region, and exhibit fundamental
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Revolutionizing Fe doped back barrier AlGaN/GaN HEMTs: Unveiling the remarkable 1700V breakdown voltage milestone Microelectron. J. (IF 2.2) Pub Date : 2024-03-16 I.V.Binola K Jebalin, S. Angen Franklin, Gifta G, Prajoon P, D. Nirmal
This research investigates the enhanced device breakdown capabilities of silicon-based AlGaN/GaN High Electron Mobility Transistors (HEMT). By incorporating various back barrier materials, a significant improvement in peak electric field and breakdown voltage is observed. Specifically, the integration of iron (Fe) doping into the Gallium Nitride (GaN) back barrier layer, combined with different back
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A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator Microelectron. J. (IF 2.2) Pub Date : 2024-03-15 Yiming Ouyang, Yihe Zhang, Huaguo Liang, Jianhua Li
In chip multiprocessor systems (CMPs), Network on Chip (NoC) has been widely used due to its advantages of favorable reusability, high reliability, and low power consumption. Recently, using NoC platforms to accelerate deep neural networks (DNNs) has become a new trend. This design can enable the intermediate computation results of DNNs to be transmitted within the chip, reducing the number of accesses
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A 22 nm CMOS 2.4 GHz 40.91 dB voltage gain RX front-end design Microelectron. J. (IF 2.2) Pub Date : 2024-03-14 Bodong Zhang, Xiao Luo, Xian Tang, Songping Mai, Xinpeng Xing, Haigang Feng
This briefing introduces a receiver (RX) front-end integrated with a virtual switch-based transmit/receive switch (TRSW) and a reconfigurable capacitor cross-coupled low noise amplifier (LNA) that employs the gain control scheme of direct shunt. Simulation and testing results indicate that the TRSW has an insertion loss of 0.2 dB and an isolation of 30 dB. The LNA achieves a maximum voltage gain of
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Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects Microelectron. J. (IF 2.2) Pub Date : 2024-03-09 Rashi Chaudhary, Rajesh Saha, Menka Yadav
This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (I), Off-current (I), Maximum transconductance
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A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS Microelectron. J. (IF 2.2) Pub Date : 2024-03-08 Heng Zhang, Xuan Guo, Ben He, Hanbo Jia, Xinyu Liu
This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising
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Ultra-wideband high gain low group delay variation amplifier for phased-array radar system Microelectron. J. (IF 2.2) Pub Date : 2024-03-07 Bofan Chen, Zhiqun Li, Zewen Xu, Jiapeng Wan, Zhennan Li, Yitong Xiong, Yan Pu
This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces a new notch for , thus extending the matching bandwidth. Staggered tuning of load impedance peaks at each stage facilitates a balance between
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Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET Microelectron. J. (IF 2.2) Pub Date : 2024-03-07 Nitish Kumar, Aakanksha Mishra, Ankur Gupta, Pushpapraj Singh
In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model is proposed with the help of a lateral electric field (E) across the inner and outer gate interfaces of the junctionless double-gate-all-around (JL-DGAA) field-effect transistor (FET). The E at the interface is obtained from the surface potential equation after solving the 3D Poisson equation with appropriate boundary
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Design and application of germanium based complementary TFET devices with step tunneling paths Microelectron. J. (IF 2.2) Pub Date : 2024-03-06 Rui Chen, Huiyong Hu, Xinlong Shi, Ruizhe Han, Peijian Zhang, Tao Liu, Liming Wang
Expanding tunneling has consistently been one of the approaches to enhance the on-state current () and performance of Tunnel Field-Effect Transistor (TFET). This paper proposes a novel structure for TFET called Step Tunneling Path TFET (STP TFET). The stepped tunneling path is achieved by preparing majority carrier channel and introducing pocket doping layers and lightly doped channel extension regions
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A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording Microelectron. J. (IF 2.2) Pub Date : 2024-03-06 Siwan Dong, Ruoyu Zhang, Chuqiang Jing, Menghan Yuan
This paper proposes a programmable gain amplifier (PGA) with common-mode voltage control for ECG recording. In order to ensure that input common-mode interference (CMI) does not deteriorate amplifier performance, a novel common-mode voltage control module is proposed, which soaks up CMI and maintains the common-mode input within the expected range. Utilizing a standard 65 nm CMOS process, our PGA runs
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A high-throughput and low-storage stereo vision accelerator with dependency-resolving strided aggregation for 8-path semi-global matching Microelectron. J. (IF 2.2) Pub Date : 2024-03-05 Yitong Rong, Xuyang Duan, Jun Han
Semi-global matching(SGM) is a well-known algorithm that generates depth maps from two images. However, due to its high computation, memory requirements and the inherent data dependency problem, implementing SGM in real-time is challenging. In this paper, we propose dependency-resolving strided cost aggregation(SCA) to resolve the data dependency problem. We also propose a cost distillation scheme
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A new CMOS-memristor based D-latch with fewer components Microelectron. J. (IF 2.2) Pub Date : 2024-03-05 Ge Shi, Chenyu Wang, Fei Qiao, Rubin Lin, Shien Wu, Yanwei Sun, Mang Shi, Jianqiang Han
In order to study the function of memristor in new devices, a new D-latch is proposed in this paper, which is composed of threshold-type memristor, transistor, resistor and NOT gate. The proposed D-latch uses fewer components than previous. The transistor controls the on-off of the signal, and NOT gate changes the resistance state of memristor. The voltage divider circuit composed of memristor and
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An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS Microelectron. J. (IF 2.2) Pub Date : 2024-03-04 Siwan Dong, Menghan Yuan, Sihao Ning
In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current
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A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS Microelectron. J. (IF 2.2) Pub Date : 2024-03-04 Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen, Qiang Li
This paper presents a low-power 16-bit 50-MS/s pipeline analog-to-digital converter (ADC). An improved switched-capacitor bias technique is proposed to reduce power consumption while maintaining excellent performance, and a novel bootstrapped switch is implemented to improve the linearity further. An INL-(integral nonlinearity) based capacitor mismatch calibration is proposed to calibrate the capacitor
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A high-pass shaped LMS algorithm based predistortion technique for fractional-[formula omitted] BB-DPLLs Microelectron. J. (IF 2.2) Pub Date : 2024-03-02 Tuan Minh Vo
In this paper, we prove that rather than the second-order modulator (DSM) as typically believed using the first-order one yields a faster convergence for the linear-piecewise predistortion technique employed in digital/time converter (DTC) based fractional- Bang-Bang digital phase-locked-loops (BB-DPLLs). We also propose a novel technique that addresses the limit-cycle issue happening in near-integer
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A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators Microelectron. J. (IF 2.2) Pub Date : 2024-02-29 Depeng Sun, Ruiqing Wang, Feng Bu, Yuan Gao, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Rong Zhou
This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, the 8.5–17.8-GHz output is covered and the phase noise is reduced by about 3 dB with the halving total equivalent inductance of the tank. Meanwhile, the clock distribution is designed to obtain 0.05–8
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An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits Microelectron. J. (IF 2.2) Pub Date : 2024-02-28 Zejia Lyu, Jizhong Shen
Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA). Benchmarked against PrimeTime PX, the proposed algorithm proficiently analyzes large-scale combinational and sequential circuits. This research begins with a power analysis algorithm for combinational circuits, focusing
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An analytical subthreshold I–V model of SiC MOSFETs Microelectron. J. (IF 2.2) Pub Date : 2024-02-26 Yi Li, Tao Zhou, Geng Jiang, Liangbin Deng, Zixuan Guo, Qiaoling Sun, Bangyong Yin, Yuqiu Yang, Junyao Wu, Huan Cai, Jun Wang, Jungang Yin, Qin Liu, Linfeng Deng
In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on
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Multi-bit per cycle true random number generator based on XOR-XNOR ring oscillator unit Microelectron. J. (IF 2.2) Pub Date : 2024-02-24 Qitian Fan, Feng Ran, Limin Yan
To achieve a fast and resource-efficient entropy source, we present a novel oscillator unit, called XOR-XNOR ring oscillator (XXRO) which consists of an XOR gate and an XNOR gate. The XXRO unit has an internal feedback loop that allows the accumulation of jitter within the unit. Connecting multiple XXRO units forms a new entropy source. We utilize the differences between the XXRO units in the entropy
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A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis Microelectron. J. (IF 2.2) Pub Date : 2024-02-24 Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad
This study investigates the effects of temperature on RF/Analog and linearity parameters using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first time. The SNC-FinFET exhibits superior performance compared to the conventional step architecture, with an enhancement of 7.2% in I (ON-current), 73.58% in I (OFF-current), excellent SS (Sub-threshold Swing) of 57.51 mV/decade
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A nanosecond-scale CuI synaptic memristor prepared by a solution-based process Microelectron. J. (IF 2.2) Pub Date : 2024-02-24 Bochang Li, Wei Wei, Li Luo, Ming Gao, Chunxiang Zhu
Owing to the synaptic behaviors and functions, memristors are intensively studied as a critical component for the neuromorphic computing system which is considered as an effective scenario to tackle the performance bottleneck existing in modern computers based on the von Neumann architecture. A novel synaptic device base on the CuI memristor prepared with a solution-based process is proposed in this
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Performance improvement for the CMOS rail-to-rail amplifier via APSO-based design and SNN’s training Microelectron. J. (IF 2.2) Pub Date : 2024-02-23 Xianming Liu, Shihong Wu, Wenrun Xiao, Chenhui Zhao, Chao Huang, Donghui Guo
This paper proposes an adaptive Particle Swarm Optimization(APSO) global search algorithm and Spiking Neural Network(SNN) surrogate model-based optimization design method for analog integrated circuits performance enhancement. The initial design parameters are calculated by numerical computation. The global design space is extended and explored using APSO in the main loop, with constraint testing ensuring
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Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture Microelectron. J. (IF 2.2) Pub Date : 2024-02-22 Sai Shirov Katta, Tripty Kumari, P.S.T.N Srinivas, Pramod Kumar Tiwari
The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high current ratio of 10 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits
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High efficiency active rectifier with low-power self-biased comparator for low-frequency piezoelectric vibration energy harvesting of AUV Microelectron. J. (IF 2.2) Pub Date : 2024-02-19 Tzung-Je Lee, Yu-Wei Liu
This paper proposes an Active Rectifier for low-frequency vibration piezoelectric (PZE) energy harvesting of Autonomous Underwater Vehicle (AUV). By using the cross-coupled NMOS transistors and active driven PMOS transistor, the turned-on resistance across the transistors could be minimized such that the voltage conversion efficiency is improved. Besides, the problem of the reverse current is avoided
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Logic cloning based approximate signed multiplication circuits for FPGA Microelectron. J. (IF 2.2) Pub Date : 2024-02-19 Abhinav Kulkarni, Messaoud Ahmed Ouameur, Daniel Massicotte
As hardware circuits become larger and more intricate, there is a growing need for approximate circuit techniques. These approaches offer a trade-off, sacrificing some system accuracy in exchange for greater hardware resource efficiency and energy conservation. In the context of FPGA-based computation-intensive arithmetic multiplication, Logic Cloning () is introduced to systematically induce controlled
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An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces Microelectron. J. (IF 2.2) Pub Date : 2024-02-19 Jiacheng Cao, Wei Xiong, Jie Lu, Peilin Chen, Jian Wang, Jinmei Lai, Miaoqing Huang
Brain–computer interfaces (BCIs) based on electroencephalogram (EEG) signals have recently gained significant attention. EEGNet is a lightweight convolutional neural network designed for EEG-based BCIs. Previous EEGNet processors are implemented with high-precision fixed-point numbers, resulting in high power consumption and resource utilization. To address these drawbacks, this paper proposes a low-precision
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An evenly-spaced-phase all-digital DLL using dual-loop SAR control Microelectron. J. (IF 2.2) Pub Date : 2024-02-16 Sijie Chen, Tingcun Wei, Nan Chen
This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly
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GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance Microelectron. J. (IF 2.2) Pub Date : 2024-02-15 Mohammad Zaid, Ahtisham Pampori, Mohammad Sajid Nazir, Yogesh Singh Chauhan
This paper introduces a novel multi-harmonic resonance approach in designing a single-ended parallel-circuit class – E/F power amplifier (PA). At its core, this innovative design integrates a novel reactance compensation technique with multi-harmonic tuning at the load, to achieve unprecedented wideband characteristics and elevated efficiency. The approach is further distinguished by the strategic
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A design method of bipolar junction transistor for high-precision remote temperature sensing Microelectron. J. (IF 2.2) Pub Date : 2024-02-12 Linfeng Wei, Wenchang Li, Tianyi Zhang, Jian Liu
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A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling nonlinearity compensation and inherent 2-b coarse ADC for MSBs decision Microelectron. J. (IF 2.2) Pub Date : 2024-02-09 Hongrui Luo, Zihao Jiao, Yang Chen, Jie Zhang, Quan Sun, Xiaofei Wang, Hong Zhang
This paper presents a high-precision, successive-approximation-register (SAR) analog-to-digital converter (ADC) with maximum input range of ±10 V for industry applications, where the wide-range input signal is sampled directly on part of the capacitive digital-to-analog converter (CDAC) via high-voltage (HV) sampling switches. An inherent 2-b coarse ADC is designed to avoid charge leakage under large