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Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs J. Electron. Test. (IF 0.9) Pub Date : 2024-04-23 Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola
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Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application J. Electron. Test. (IF 0.9) Pub Date : 2024-04-17 Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava
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An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis J. Electron. Test. (IF 0.9) Pub Date : 2024-04-16 Yuling Shang, Songyi Wei, Chunquan Li, Xiaojing Ye, Lizhen Zeng, Wei Hu, Xiang He, Jinzhuo Zhou
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A Survey and Recent Advances: Machine Intelligence in Electronic Testing J. Electron. Test. (IF 0.9) Pub Date : 2024-04-15 Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
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Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm J. Electron. Test. (IF 0.9) Pub Date : 2024-04-12 Bahman Arasteh, Sahar Golshan, Shiva Shami, Farzad Kiani
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Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission J. Electron. Test. (IF 0.9) Pub Date : 2024-04-04 Rongxing Cao, Yan Liu, Yulong Cai, Bo Mei, Lin Zhao, Jiayu Tian, Shuai Cui, He Lv, Xianghua Zeng, Yuxiong Xue
As the central control component in aerospace products, SRAM-based FPGA finds extensive application in space. In its operational context, the space radiation environment introduces single event effect (SEE) and space electrostatic discharge effect (SESD) in FPGAs. This paper investigates SEE and SESD in SRAM-based FPGA using an integrated simulation method that combines device-level and circuit-level
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Instant Test and Repair for TSVs using Differential Signaling J. Electron. Test. (IF 0.9) Pub Date : 2024-04-03
Abstract A faulty Through Silicon Via (TSV) could spoil a 3D IC and cause hefty loss as the potentially expensive known-good-dies bonded together must be discarded. This work presents a Fault-tolerant TSV scheme to avoid such a disastrous situation. Our method uses two differential TSVs for each binary signal to be transmitted. Compared to the previous Fault-tolerant TSV schemes, our test and repair
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An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET J. Electron. Test. (IF 0.9) Pub Date : 2024-03-28 Baojun Liu, Li Cai, Chuang Li
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A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing J. Electron. Test. (IF 0.9) Pub Date : 2024-03-23
Abstract Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty
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Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs J. Electron. Test. (IF 0.9) Pub Date : 2024-03-21 Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edwar J. Patiño Núñez, Robert Limas, Matteo Sonza Reorda
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Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach J. Electron. Test. (IF 0.9) Pub Date : 2024-03-20 Hala Ibrahim, Haytham Azmi, M. Watheq El-Kharashi, Mona Safar
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Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees J. Electron. Test. (IF 0.9) Pub Date : 2024-03-07
Abstract Biological assays around “lab-on-a-chip (LoC)” are required in multiple concentration (or dilution) factors, satisfying specific sample concentrations. Unfortunately, most of them suffer from non-locality and are non-protectable, requiring a large footprint and high purchase cost. A digital geometric technique can generate arbitrary gradient profiles for digital microfluidic biochips (DMFBs)
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A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches J. Electron. Test. (IF 0.9) Pub Date : 2024-03-02 Hui Xu, Xuewei Qin, Ruijun Ma, Chaoming Liu, Shuo Zhu, Jun Wang, Huaguo Liang
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Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance J. Electron. Test. (IF 0.9) Pub Date : 2024-03-02
Abstract The recent expansion of the Internet of Things (IoT) owes a lot to the significant contribution of the 6LoWPAN protocol, which has been extensively employed in low-power and lossy networks. To facilitate communication in 6LoWPAN networks, the Internet Engineering Task Force (IETF) has suggested the usage of the Routing Protocol for Low-Power and Lossy Networks (RPL). Despite its usefulness
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A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements J. Electron. Test. (IF 0.9) Pub Date : 2024-02-27 Zhengfeng Huang, Zishuai Li, Liting Sun, Huaguo Liang, Tianming Ni, Aibin Yan
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Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems J. Electron. Test. (IF 0.9) Pub Date : 2024-02-27 M. N. Saranya, Rathnamala Rao
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Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations J. Electron. Test. (IF 0.9) Pub Date : 2024-02-27 Victor Champac, Hector Villacorta, R. Gomez-Fuentes, Fabian Vargas, Jaume Segura
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Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration J. Electron. Test. (IF 0.9) Pub Date : 2024-02-24 Shifeng Yu, Junjie Dai, Junhui Li
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Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration J. Electron. Test. (IF 0.9) Pub Date : 2024-02-21 Huang Linsen
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General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme J. Electron. Test. (IF 0.9) Pub Date : 2024-01-09 Shun-Hua Yang, Shi-Yu Huang
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Effective Software Mutation-Test Using Program Instructions Classification J. Electron. Test. (IF 0.9) Pub Date : 2024-01-09 Zeinab Asghari, Bahman Arasteh, Abbas Koochari
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Performance Efficient and Fault Tolerant Approximate Adder J. Electron. Test. (IF 0.9) Pub Date : 2023-12-11 Asma Iqbal, Syed Affan Daimi, K. Manjunatha Chari
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Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field J. Electron. Test. (IF 0.9) Pub Date : 2023-12-07 Shouhong Chen, Tao Wang, Zhentao Huang, Xingna Hou
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A Survey of PCB Defect Detection Algorithms J. Electron. Test. (IF 0.9) Pub Date : 2023-12-01 Gayathri Lakshmi, V. Udaya Sankar, Y. Siva Sankar
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Efficient Fault Detection by Test Case Prioritization via Test Case Selection J. Electron. Test. (IF 0.9) Pub Date : 2023-11-22 J. Paul Rajasingh, P. Senthil Kumar, S. Srinivasan
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Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection J. Electron. Test. (IF 0.9) Pub Date : 2023-11-02 Zhenyu Zhao, Xin Chen, Yufan Lu
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MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms J. Electron. Test. (IF 0.9) Pub Date : 2023-10-24 Priyajit Bhattacharya, Rahul Bhattacharya, Himasree Deka
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Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN J. Electron. Test. (IF 0.9) Pub Date : 2023-10-12 Ying-Chun Xiao, Feng Zhu, Shengxian Zhuang, Yang Yang
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Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model J. Electron. Test. (IF 0.9) Pub Date : 2023-09-22 Richa Sharma, G. K. Sharma, Manisha Pattanaik, V. S. S. Prashant
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Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns J. Electron. Test. (IF 0.9) Pub Date : 2023-09-16 Ling Zhang
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A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells J. Electron. Test. (IF 0.9) Pub Date : 2023-09-15 Joseph Herbert Mitchell-Moreno, Guillermo Espinosa Flores-Verdad
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Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection J. Electron. Test. (IF 0.9) Pub Date : 2023-09-07 Tapobrata Dhar, Ranit Das, Chandan Giri, Surajit Kumar Roy
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Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System J. Electron. Test. (IF 0.9) Pub Date : 2023-08-30 Vinod S Chippalkatti, Rajashekhar C Biradar, Venkatesh Shenoy, P Udayakumar
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Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network J. Electron. Test. (IF 0.9) Pub Date : 2023-08-11 R. Saravana Ram, M. Lordwin Cecil Prabhaker
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New Second-order Threshold Implementation of Sm4 Block Cipher J. Electron. Test. (IF 0.9) Pub Date : 2023-08-04 Tianyi Shao, Bohua Wei, Yu Ou, Yongzhuang Wei, Xiaonian Wu
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E3C Techniques for Protecting NAND Flash Memories J. Electron. Test. (IF 0.9) Pub Date : 2023-07-01 Shyue-Kung Lu, Zeng-Long Tsai
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A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm J. Electron. Test. (IF 0.9) Pub Date : 2023-06-20 Bahman Arasteh, Farhad Soleimanian Gharehchopogh, Peri Gunes, Farzad Kiani, Mahsa Torkamanian-Afshar
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Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems J. Electron. Test. (IF 0.9) Pub Date : 2023-06-20 Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr, Rafael I. Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei A. Guazzelli, Nilberto H. Medina, Paulo F. Butzen
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Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection J. Electron. Test. (IF 0.9) Pub Date : 2023-06-16 Vijaypal Singh Rathor, Deepak Singh, Simranjit Singh, Mohit Sajwan
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Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing J. Electron. Test. (IF 0.9) Pub Date : 2023-06-03 Benedikt Jooß, Dieter Schramm
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Incomplete Testing of SOC J. Electron. Test. (IF 0.9) Pub Date : 2023-05-29 Kunwer Mrityunjay Singh, Jatindra Deka, Santosh Biswas
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Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations J. Electron. Test. (IF 0.9) Pub Date : 2023-05-25 K. Coulié, H. Aziza, W. Rahajandraibe
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A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits J. Electron. Test. (IF 0.9) Pub Date : 2023-05-24 Pradeep Kumar Biswal
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BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems J. Electron. Test. (IF 0.9) Pub Date : 2023-05-18 Sabyasachi Deyati, Barry Muldrey, Abhijit Chatterjee
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Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets J. Electron. Test. (IF 0.9) Pub Date : 2023-05-09 Zhengfeng Huang, Hao Wang, Dongxing Ma, Huaguo Liang, Yiming Ouyang, Aibin Yan
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Design of INV/BUFF Logic Locking For Enhancing the Hardware Security J. Electron. Test. (IF 0.9) Pub Date : 2023-05-05 R. Naveenkumar, N. M. Sivamangai, A. Napolean, S. Sridevi Sathya Priya, S. V. Ashika
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Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network J. Electron. Test. (IF 0.9) Pub Date : 2023-04-29 Wenjing Tang, Jing Su, Yuchan Gao
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Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift J. Electron. Test. (IF 0.9) Pub Date : 2023-04-25 Hui Jiang, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore Manikas
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Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation J. Electron. Test. (IF 0.9) Pub Date : 2023-04-25 Tai Song, Zhengfeng Huang, Xiaohui Guo, Krstic Milos
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Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm J. Electron. Test. (IF 0.9) Pub Date : 2023-03-29 Raghavendra Kumar Sakali, Noor Mahammad Shak
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Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications J. Electron. Test. (IF 0.9) Pub Date : 2023-03-28 Tommaso Melis, Emmanuel Simeu, Etienne Auvray, Luc Saury
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On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits J. Electron. Test. (IF 0.9) Pub Date : 2023-03-27 H. El Badawi, F. Azais, S. Bernard, M. Comte, V. Kerzerho, F. Lefevre
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A Tunable Concurrent BIST Design Based on Reconfigurable LFSR J. Electron. Test. (IF 0.9) Pub Date : 2023-03-06 Ahmad Menbari, Hadi Jahanirad
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Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation J. Electron. Test. (IF 0.9) Pub Date : 2023-02-27 Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
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Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey J. Electron. Test. (IF 0.9) Pub Date : 2023-02-28 Bahareh Asadi, Syed Maqsood Zia, Hamza Mohammed Ridha Al-Khafaji, Asghar Mohamadian
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A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing J. Electron. Test. (IF 0.9) Pub Date : 2023-02-21 Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
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Multiple Retest Systems for Screening High-Quality Chips J. Electron. Test. (IF 0.9) Pub Date : 2023-02-20 Chung-Huang Yeh, Jwu E. Chen
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Identifying Resistive Open Defects in Embedded Cells under Variations J. Electron. Test. (IF 0.9) Pub Date : 2023-02-09 Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich
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DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram J. Electron. Test. (IF 0.9) Pub Date : 2023-02-03 Xiaozhi Du, Jinjin Zhang, Kai Chen, Yanrong Zhou